Pokey decap

[ijor]

On 11/30/2022 at 3:19 AM, phaeron said:

Necrobumping again for an erratum, the middle tap for the 5-bit polynomial should be at x^3 instead of x^2 ...

 

You are correct. Thanks for reporting the error (a silly typo).

[ijor]

Updated schematics fixing the error mentioned above:

 

PokeyReSchem-12.pdf

 

I would appreciate if a moderator let me edit the first post of the thread. Thanks.

[Albert]

2 hours ago, ijor said:

I would appreciate if a moderator let me edit the first post of the thread. Thanks.

You can now edit the first post in this thread indefinitely.

 

 ..Al

[ijor]

31 minutes ago, Albert said:

You can now edit the first post in this thread indefinitely.

 

Thanks Al!

[Albert]

1 minute ago, ijor said:

Thanks Al!

You're welcome!

[+ZuluGula]

How many transistors are in Pokey, or other LSI chips like Anic and GTIA?

[Keatah]

On 12/1/2022 at 7:05 AM, Vyvyan B. said:

You'd think that by now you'd be able to stick one of these old chips into a reader, analyze it with some AI and crank out a replacement FPGA in no time flat.

A portion of the process can be done automatically. Involves decapping and machine vision to read the layers.

 

In time perhaps AI would be able to observe how the real part behaves in-circuit and do the job. But not today.

Edited December 2, 2022 by Keatah

[ijor]

3 hours ago, ZuluGula said:

How many transistors are in Pokey, or other LSI chips like Anic and GTIA?

Pokey and GTIA have in the order of 5.000 transistors, each one. ANTIC has approx 8.000 total transistors, this includes something like 2.500 transistors just for the RAM.

[+Stephen]

4 hours ago, ijor said:

Pokey and GTIA have in the order of 5.000 transistors, each one. ANTIC has approx 8.000 total transistors, this includes something like 2.500 transistors just for the RAM.

Is it really that high?  For some reason I had it in my head that they were about equal to 6502, being some 3,500ish.  No idea where this came from though.

[Rybags]

My thought was in the order of 4,500 for all three.  We should remember 6502 is a 1975 release - Wiki article says 3510 transistors.

I theorised that Antic/GTIA were probably seperate because the process of the day didn't allow both together easily.

I would guess there was probably working versions of the three in early 1979.  Moore's law would say you'd be halfway to the next doubling of transistor count by the time the computers were released.

That said though, the 68000 was a 1979 release and supposedly has 68000 transistors though it's in a somewhat bigger chip package.

 

I guess Atari being themselves they probably had surplus stock of the custom chips to the point where a process shrink didn't make any sense.  In the meantime there was also the NMOS to CMOS move so possibly there could be issues there, esp GTIA since it uses internal delay taps for colour generation.

[Keatah]

Would a process shrink have been technically beneficial? I don't see a need (for the shrink) because space was not at a premium. Neither power consumption or heat dissipation were issues either.

[Rybags]

I guess CGIA would have used a process shrink.

For the chips as individuals there would have been little advantage since the final size for a 40 pin DIP is the same whether it's 6 um or 3 um fab.

But a shrink should mean more dies per wafer which should reduce costs.

 

Maybe they did a shrink at one point and we just don't know it?  A decap of something like one of those faulty late 80s Eastern Euro GTIAs might help there.

[ijor]

8 hours ago, Stephen said:

Is it really that high?  For some reason I had it in my head that they were about equal to 6502, being some 3,500ish.  No idea where this came from though.

 

The 6502 actually has 4,500 transistors or so. The 3,500 figure mentioned in some places doesn't count pull up transistors. I included pull-ups on the count. So POKEY and GTIA are about the same "size" as the 6502. Again, what makes the difference about ANTIC is the internal RAM.

 

8 hours ago, Rybags said:

I theorised that Antic/GTIA were probably seperate because the process of the day didn't allow both together easily.

 

The main reason to use two separate chips was probably the limitation of 40 pins per chip.

[Rybags]

Yeah, CGIA has 48 of which 2 are superfluous in later times - NC and RNMI which wasn't used on XL.

They could possibly have used the Secam GTIA trick to serially read the TRIG lines which could have freed up another few pins.

Still doesn't bring it to 40 though.

 

Just realised - CGIA has CLUM which eliminates the need for external buffering and luma generation - I would guess that would probably eliminate the annoying luma drop problem when you go from something like level 7 to 8.

[+ZuluGula]

Couple days ago I had a discussion with a few friends if it would be possible for a hobbyist to produce real Pokeys or other 70's ICs, if he had access to the tools used back then. Turns out, that there's a guy, Sam Zeloof, who made 1200 transistors IC in his parents garage with tools he got of ebay. So we are not far away from making Pokeys in our garages again

[+DjayBee]

28 minutes ago, ZuluGula said:

Couple days ago I had a discussion with a few friends if it would be possible for a hobbyist to produce real Pokeys or other 70's ICs, if he had access to the tools used back then. Turns out, that there's a guy, Sam Zeloof, who made 1200 transistors IC in his parents garage with tools he got of ebay. So we are not far away from making Pokeys in our garages again

The logical next step is then to build a FRUIT 1 computer in a garage and start an empire. 😜

[+ZuluGula]

Anyone can build FRUIT computers, but not many can make the necessary components to do it. The current chip shortage is good example of it. 

[DirtyMcDingus]

I just found this place and wish I would have found it a few months ago. I have been using the 1.0 version of the schematic to build an FPGA POKEY replacement. I have been writing about it as I go along. I just finished writing the last bit of HDL. I found some schematic issues as I was working. One of them was the error in the poly5 hardware pointed out in this topic. I also found that the serial receiver hardware did not work right without modifying the Serial Data In PLA. ijor, are you still monitoring this topic? I want to share my findings with you and see if it can be confirmed in the die photos. I don't know anything about understanding that stuff. The error is also in the original schematics. Here is how I had to change it to get it to work:

Thanks!

[ijor]

12 hours ago, DirtyMcDingus said:

I also found that the serial receiver hardware did not work right without modifying the Serial Data In PLA. ijor, are you still monitoring this topic? I want to share my findings with you and see if it can be confirmed in the die photos. I don't know anything about understanding that stuff. The error is also in the original schematics. Here is how I had to change it to get it to work:

At first glace it seems to me that there is no such error and the schematics, both Atari original one and mine, are ok. I will double check it just in case.

Edited March 4, 2023 by ijor

[ijor]

16 hours ago, DirtyMcDingus said:

I also found that the serial receiver hardware did not work right without modifying the Serial Data In PLA

 

Ah, there is indeed a mistake there, but it is not exactly as you "fixed" it. There is a missing connection with "sdiBusy" at the PLA's last row. That connection is present in the original schematics.

 

I will fix it and post an update. Thanks for the report.

[DirtyMcDingus]

Thanks ijor! I have a handful of minor things I found that I think need to be corrected. I can share them with you if you are interested.

[ijor]

16 minutes ago, DirtyMcDingus said:

Thanks ijor! I have a handful of minor things I found that I think need to be corrected. I can share them with you if you are interested.

 

Sure. Please post any comment, mistake or question here. I will wait for your post before posting an updated schematics.

 

[DirtyMcDingus]

I made the change you pointed out and it worked. It generates the state machine as the solution I implemented.

 

Here are the other minor things I noticed. I'm assuming they are just typos:

Both the above items are in the serial portion of the schematics.

The issue below is in the address decoder. The address 6 line has not circles on it.

 

Also, I think this is not correct. This also shows up in the original schematic but it seems wrong:

This is the only place where the init signal is not asynchronous when interfacing with a logic gate clock coupled with clock phase 1. The init signal originates from a gate clock coupled with clock phase 1. I don't think two gates with the same clock phase are supposed to feed into each other. Of course I'm not an expert on NMOS logic...

 

Other than these minor things. Everything else seems awesome. I am currently working on POKEY replacements and I have finished making all the various modules and verified they work in the simulator. I'm in the process of integrating them into the top level. Its open source and can be found here:

https://github.com/nmikstas/atari_pokey

 

Thanks for all your awesome work, ijor!

[ijor]

10 hours ago, DirtyMcDingus said:

Here are the other minor things I noticed. I'm assuming they are just typos:

 

Yeah, the inverters above are indeed swapped.

 

10 hours ago, DirtyMcDingus said:

No, this was correct. The async input is the output of the clocked NOR.

 

Quote

The issue below is in the address decoder. The address 6 line has not circles on it.

Right. Four couplers (circles) got missing.

 

 

10 hours ago, DirtyMcDingus said:

Also, I think this is not correct. This also shows up in the original schematic but it seems wrong:

This is the only place where the init signal is not asynchronous when interfacing with a logic gate clock coupled with clock phase 1. The init signal originates from a gate clock coupled with clock phase 1. I don't think two gates with the same clock phase are supposed to feed into each other. Of course I'm not an expert on NMOS logic...

 

No. It is correct. The Init signal is actually not fully synchronous to either 1 or 2 phase. It is possible to connect two gates clocked by the same phase. By most purposes that would be the same as connecting them asynchronously. But again, this is not exactly the case here.

 

Thanks a lot for the feedback. I will post updated schematics later.

 

 

 

 

[ijor]

Updated schematics (V 1.3) are posted at the first post of this thread.