Some TIA schematic questions

[SeaGtGruff]

Okay, here are pictures to show what's confusing me about the AUDC section.

 

First, here's the AUDV register from sheet 4. Note that each "bit box" is labeled with an "L" to specify what type of circuit (or collection of circuits) it is. And the drawing makes sense-- the two inputs to each NOR gate must both be low for the output to be high. So if D0 is 1 (or D1, or D2, or D3), we want to use its inverse for the input:

 

 

And here's the detail for the "L" circuit or device, from sheet 1:

 

 

Now here's the AUDF register from sheet 4. The output lines are swapped-- the inverted output is at the top:

 

 

And here's the detail, also from sheet 4:

 

 

Finally, here's the AUDC register and its associated pull-up or pull-down grid, from sheet 4:

 

 

If the top output lines are normal, the circles on the grid make sense-- at least, if the grid works the same way as the grids do on the other sheets. But that would mean they forgot to label the boxes with an "L," which seems hard to believe, since they were careful to include the "L" label in all the other appropriate places throughout the schematics. The fact that there's no "L" label seems to imply that these boxes are like the ones of the AUDF register, with the inverted output on the top. If that's correct, then the logic of the AUDC grid needs to be reversed, right?

 

Michael

 

 

 

[SeaGtGruff]

The counters reset when they reach the programmed count value. The left set of boxes is the AUDFx register, each bit of which is equipped with inverted and non-inverted outputs. Each stage of the counter is likewise equipped with inverted and non-inverted outputs. The leftmost vertical line through the larger, right-side, set of boxes, will be pulled to ground if any counter bit disagrees with its corresponding AUDFx bit. That signal is delayed by two pass gates and then fed vertically, between the two clock wires, as one of the three-inputs to a NOR gate to clear all the counter stages.

Okay, so I worked through an example-- AUDF0 = %00101, the same example I used before, but this time starting with the reset line triggering the counter to go back to %00000. I had the bits on the left side of the counter inverted, because I didn't understand how the comparator works. If any of the bits on the right side of the comparator are the *same* as the bits on the left side, the output will be 0. Once the counter reaches the programmed value, the bits on the right side of the comparator will all be *different* than the bits on the left side, and the output will go high, which will trigger the reset again on the next phase 2 audio clock. So the comparator works like the horizontal line of a pull-up or pull-down grid (I never know which is the correct term to use there). If the two sides are equal, that comparison is true or 1, and the output will be low. But if the two sides are different all along the comparators, they're all false (0), and the output will be high.

 

So the counts are as follows:

 

AUDF0 = %00000 -> %11111

%00000 -> all different, output 1, reset

%00000 -> all different, output 1, reset

 

AUDF0 = %00001 -> %11110

%00001 -> all different, output 1, reset

%00000 -> not all different, output 0

%00001 -> all different, output 1, reset

%00000 -> not all different, output 0

 

AUDF0 = %00010 -> %11101

%00010 -> all different, output 1, reset

%00000 -> not all different, output 0

%00001 -> not all different, output 0

%00010 -> all different, output 1, reset

%00000 -> not all different, output 0

%00001 -> not all different, output 0

 

AUDF0 = %00011 -> %11100

%00011 -> all different, output 1, reset

%00000 -> not all different, output 0

%00001 -> not all different, output 0

%00010 -> not all different, output 0

%00011 -> all different, output 1, reset

%00000 -> not all different, output 0

%00001 -> not all different, output 0

%00010 -> not all different, output 0

 

etc.

 

That makes a lot more sense! Thank you for clearing it up!

 

Michael

[ijor]

If by PLAs (programmable logic arrays?) you mean the grid of horizontal and vertical lines shown below the 6-bit LFSR (horizontal sync counter)-- shown in a previous post-- then yes, those are the circles I meant. They're also shown in the address decode section and collision detection section on sheet 2, as well as in the audio control section on sheet 4. I understand how they work in most of those places-- like a NOR-- and that they're used with pull-up or pull-down resistors. In supercat's reply, he says they're transistors, and a pair of explanatory comments in the address decode section on sheet 2 calls them "pull-downs," but I didn't know if they had another name (like "open collector"?).

 

They do are pulldowns (pullups don't work very well with NMOS logic). And yes, they are logically a wide (multiple inputs) NOR, and yes, you might say that each circle denotes an open-drain inverter. Everything is actually the same thing.

 

Those grids are called PLAs, but in these devices they are mostly simple PLAs (just one plane), and in some cases they are actually just ROMs. But again, this is just a matter of how you look at this. A PLA is equivalent to an array of wide NORs, just conveniently packed.

 

Let's look at the WRITE ADDRESS DECODE PLA on sheet 2. The inputs to this PLA are the 14 horizontal lines. The outputs are the 45 columns. Each column is one wide NOR (probably all here are 8 inputs NOR). The circles signals the respective inputs (pulldowns) for the NOR corresponding to each column. The pullups for all the NOR columns are drawn at the bottom (the resistor symbol).

 

 

I've watched an animated GIF of a simple flip-flop in Wikipedia, which helped a great deal,

 

I am sure it helps, but be careful, it also can be misleading. There are usually no strict flip-flops in these ICs. A full flip-flop was almost prohibitive on those old ICs. In almost all cases they used some other simpler circuits, many times just async latches.

 

But I was getting lost when I tried to follow the internal workings of the /S-/R flip-flops, even breaking it down into half cycles.

 

S-R latches are usually asyncronous. They don't have a clock, or phase concept. Sometimes their respective inputs might be syncronous, but not always. Either way, the behaviour of the actual latch is asyncronous.

[SeaGtGruff]

But that would mean they forgot to label the boxes with an "L," which seems hard to believe, since they were careful to include the "L" label in all the other appropriate places throughout the schematics.

... or maybe not. As far as I can tell, the "L" label is shown everywhere it's appropriate on all five sheets, and any boxes that are unlabeled have a closeup of the detail for that type of box shown on the same sheet. But there's one other place where boxes are left unlabeled when they probably should be labeled with an "L"-- the latches for D6 and D7 of the VBLANK register, depicted on sheet 5. There are eight other boxes on sheet 5 that are clearly labeled with an "L"-- and five of them are immediately to the left of the latches for D6 and D7 of the VBLANK register-- so it's kind of odd that the person(s) preparing the schematics simply forgot to write an "L" on these two boxes, and that no one else who proofread or revised the schematics over the years ever thought to correct that oversight. Yet it's clear from the names of the signals coming out of these two boxes that the top output is normal, and the bottom output is inverted. So I guess I'll conclude that the boxes of the AUDC0 register on sheet 4 *should* be labeled with an "L"-- since that makes the audio control PLA make sense-- but that, for whatever reason, the "L" label got left out.

 

Michael

[SeaGtGruff]

I finally worked through the flip-flops that generate the phase 1 and 2 horizontal clocks! I think I was trying to make it too complicated before, thinking that all the outputs should toggle at the same time. But they stay the same when the CLK is low, and take turns toggling when the CLK is high-- first one flip-flop toggles, then (one CLK cycle later) the other flip-flop toggles. So when the output from the two flip-flops goes through the NOR gates that generate the two horizontal clocks, it comes out as follows:

 

OSC = 10101010101010101010101010101010

CLK = 10101010101010101010101010101010

Hphi1 = 11000000110000001100000011000000

Hphi2 = 00001100000011000000110000001100

 

I already knew that's what they look like, from the timing diagrams in the TIA documentation-- but it's nice to finally be able to work it out for myself.

 

Also, strobing RSYNC resets the flip-flops, and they start with Hphi1 high.

 

Michael