GTIA decap

[ivop]

6 hours ago, ijor said:

If by pulling down you mean that you expected something like a weak resistance to ground, that's not how open drain works. It shouldn't produce any bus contention as long as all other gates driving the same signal are also open drain.

Yes. I misread the schematic and swapped to long lines. That's what you get without a hard copy. Looks like the whole rD0 (and rD1,2,3) are open drain, so no bus contention will occur.

 

6 hours ago, ijor said:

Anyway, please open a separate thread for issues not specific to GTIA, or the Atari chipset for that matter. Thanks.

Sorry, will do that.

 

On page 4 of the GTIA schematics, in the lower left corner there is a large triangle that is used above for reading the databus. The detailed schematic pins do not line up with when they are in use (like other details do). I assume IN as at the top of the triangle and OD is at the bottom. Is that correct?

 

[ivop]

2 hours ago, ivop said:

On page 4 of the GTIA schematics, in the lower left corner there is a large triangle that is used above for reading the databus. The detailed schematic pins do not line up with when they are in use (like other details do). I assume IN as at the top of the triangle and OD is at the bottom. Is that correct?

Sorry, I meant top (IN) and right side (OD).

 

Edit: here's the part I mean (inlined a usage example):

 

Edited December 28, 2023 by ivop

[ivop]

I have solved it yet. Left is OUT, top is OD (clock signal based on RW, CS1 and nPhi2), right is IN. Works correctly in simulation now.

Interesting to see that internally the data bus bits 4-7 are always pulled low during a read. It never occurred to me that none of the GTIA read registers use more than 4 bits.

[ijor]

5 hours ago, ivop said:

On page 4 of the GTIA schematics, in the lower left corner there is a large triangle that is used above for reading the databus. The detailed schematic pins do not line up with when they are in use (like other details do). I assume IN as at the top of the triangle and OD is at the bottom. Is that correct?

This is the standard notation for a tri-state buffer. The signals are obvious in the context. OD stands for Output Disable, which obviously is the control signal common to all databits and coming from the combination of Chip Select and RW external pins.

[ijor]

18 hours ago, ivop said:

Interesting to see that internally the data bus bits 4-7 are always pulled low during a read. It never occurred to me that none of the GTIA read registers use more than 4 bits.

Yes, this was probably by design. The tri-state buffer is pretty big. Four less of those buffers is a significant saving.