kevtris Posted March 4, 2012 Share Posted March 4, 2012 Well I finally finished my "mega" document on mappers (bankswitching) and various pieces of peripheral hardware. In it is all the mappers I know about, and the Supercharger, Supercharger demo unit, the tape format for same, and the Compumate. If there's anything I missed lemme know and I will add it. http://blog.kevtris....0%20Mappers.txt 5 Quote Link to comment Share on other sites More sharing options...
GroovyBee Posted March 4, 2012 Share Posted March 4, 2012 Thanks for the updated list. Quote Link to comment Share on other sites More sharing options...
Joe Musashi Posted March 4, 2012 Share Posted March 4, 2012 That's a great document. Thanks for posting! I just had a quick read, but one thing that could also be added would be some info about the 'Super Chip', i.e. F4+SC etc. mappers. Quote Link to comment Share on other sites More sharing options...
Kroko Posted March 4, 2012 Share Posted March 4, 2012 (edited) Great Document ! Thanks ! Edited March 4, 2012 by Kroko Quote Link to comment Share on other sites More sharing options...
kevtris Posted March 4, 2012 Author Share Posted March 4, 2012 That's a great document. Thanks for posting! I just had a quick read, but one thing that could also be added would be some info about the 'Super Chip', i.e. F4+SC etc. mappers. Oh yeah, I knew I forgot something! Quote Link to comment Share on other sites More sharing options...
+batari Posted March 7, 2012 Share Posted March 7, 2012 As for 4A50, writes and reads to the same memory location are handled by an ingenious method called "magic writes." I'm not an expert on them, but as I understand it requires a FPGA or other hardware with bus hold circuitry (which provides a weak pullup/pulldown to the last logic level asserted on the bus). As I understand, it works like this: Pretend the access is a read for the first part of the cycle - fetch the data and put it on the bus. Then, float the bus before any contention occurs (writes don't use the bus until late in the cycle.) Then, late in the cycle, pretend the access is a write. Grab the value, store it to cart RAM. If the access was actually a read, the bus hold will keep the value active so the 6507 can fetch it. And, the same value will be written back to cart RAM. If the access was actually a write, the 6507 will override the bus hold circuitry, and the value will be written to cart RAM. Pretty clever, huh? (oh, and I think this is right, but anyone correct me if I'm wrong!) Quote Link to comment Share on other sites More sharing options...
Tjoppen Posted March 9, 2012 Share Posted March 9, 2012 Do the F8, F6 and F4 mappers have any reset circuitry? In other words, do they start on a random bank or is there a RC thing on /RST to ensure the latch is inited to the zeroth bank? For Minutes and a Bit I assumed F8 starts on a random bank and put a jump to the bank 0 in bank 1's Start. I've seen demos assume otherwise (probably due to testing on a Harmony). Quote Link to comment Share on other sites More sharing options...
Wickeycolumbus Posted March 10, 2012 Share Posted March 10, 2012 Great update, thanks a lot! I've been unable to find detailed info about the supercharger, supercharger demo unit, or compumate, so those should be a good read. Another thing that may be worth mentioning is the DPC+ (homebrew update of the DPC). Quote Link to comment Share on other sites More sharing options...
SeaGtGruff Posted March 10, 2012 Share Posted March 10, 2012 Do the F8, F6 and F4 mappers have any reset circuitry? In other words, do they start on a random bank or is there a RC thing on /RST to ensure the latch is inited to the zeroth bank? For Minutes and a Bit I assumed F8 starts on a random bank and put a jump to the bank 0 in bank 1's Start. I've seen demos assume otherwise (probably due to testing on a Harmony). They start up in a random bank. Quote Link to comment Share on other sites More sharing options...
Thomas Jentzsch Posted March 10, 2012 Share Posted March 10, 2012 Very nice summary. BTW: Its "Boulder Dash" Quote Link to comment Share on other sites More sharing options...
+stephena Posted March 11, 2012 Share Posted March 11, 2012 What excellent timing. I just did a search for an explanation of the CompuMate format (for addition to Stella), and it pointed to this page Quote Link to comment Share on other sites More sharing options...
+stephena Posted March 11, 2012 Share Posted March 11, 2012 There looks to be a problem in the CompuMate explanation. First, it mentions 1K of RAM in some places and 2K in another; there is actually 2K. Second, the RAM area is $1800 - $1FFF, not $0000 - $17FF. Quote Link to comment Share on other sites More sharing options...
+stephena Posted March 17, 2012 Share Posted March 17, 2012 I asked about this in another thread, but I guess it's somewhat related to this too. Any chance someone has more info on the CompuMate for improving its emulation in Stella? Specifically, how to communicate with the cassette player for loading/saving your own files, as well as accessing the SongMate and PictureMate tapes?? Quote Link to comment Share on other sites More sharing options...
kevtris Posted March 21, 2012 Author Share Posted March 21, 2012 Well I updated the things mentioned so far, except for the A450 and DPC+ stuff since I have not implemented them yet into my FPGA 2600. I updated the Compumate stuff, and you're right. I looked at the schematic of it I drew out and RAM's at 1800-1FFF. There's a huge chain of NAND gates used to generate its chip enable and I got 1 extra inversion in there. I can document the Gameline modem, too... but I am wonder how useful this would be. I own several and have one taken apart, and I dumped the ROM on it awhile back. I also have VHS footage somewhere of the menu and it loading and running games. Oh yeah, I should add information on how the atarivox works too. Also, does anyone have ROM images I can use to test some of these homebrew mappers? I want to make sure my FPGA implementations work, and to verify my documentation is correct. I need examples for the following: 0840 econobanking MC megacart X07 Atariage 4A50 DPC+ I will update the posted version after I add a few more things. Quote Link to comment Share on other sites More sharing options...
Wickeycolumbus Posted March 21, 2012 Share Posted March 21, 2012 Also, does anyone have ROM images I can use to test some of these homebrew mappers? I want to make sure my FPGA implementations work, and to verify my documentation is correct. I need examples for the following: 0840 econobanking MC megacart X07 Atariage 4A50 DPC+ I will update the posted version after I add a few more things. I wrote a bunch of demos a while back, 0840, x07, and 4A50 are attached to this post: http://www.atariage....ost__p__1883110 The 4A50 demo probably isn't too useful because as far as I remember, it doesn't very many of the features. Supercat's Ruby Runner is a much better choice: http://www.atariage....obile-monsters/ For x07, there's also this Mega Boy conversion: http://www.atariage....44#entry1547344 There's DPC+ stuff here: http://www.atariage....pc-programming/ I don't think the MC format has ever been used. I tried doing a demo once, and couldn't get it to work properly. Not really sure what happened with that. You may also want to take a look at the new FA2 method being used in Star Castle: http://www.atariage....astle-playable/ Quote Link to comment Share on other sites More sharing options...
+stephena Posted March 21, 2012 Share Posted March 21, 2012 I don't think the MC format has ever been used. I tried doing a demo once, and couldn't get it to work properly. Not really sure what happened with that. If you were using Stella to test an MC cart, it could explain why you couldn't get it to work. MC has never been tested in Stella, since I don't have any test ROMs. In fact, I just noticed I added this comment to the top of the CartMC class: // TODO - much more testing of this scheme is required // No test ROMs exist as of 2009-11-08, so we can't be sure how // accurate the emulation is // Bankchange and RAM modification cannot be completed until // adequate test ROMs are available // TODO (2010-10-03) - support CodeAccessBase functionality somehow Quote Link to comment Share on other sites More sharing options...
+stephena Posted March 21, 2012 Share Posted March 21, 2012 I forgot to mention that viewing the various CartXXX header files in the Stella codebase may also give you extra info for your document. Some of it even came from older versions of this document http://stella.svn.sf.net/viewvc/stella/trunk/src/emucore/ Quote Link to comment Share on other sites More sharing options...
+stephena Posted March 21, 2012 Share Posted March 21, 2012 Well I updated the things mentioned so far, except for the A450 and DPC+ stuff since I have not implemented them yet into my FPGA 2600. I updated the Compumate stuff, and you're right. I looked at the schematic of it I drew out and RAM's at 1800-1FFF. There's a huge chain of NAND gates used to generate its chip enable and I got 1 extra inversion in there. If you can find any documentation on how the CompuMate 'talks' to the cassette player, that would be great. Emulating the CompuMate itself is relatively easier (moreso because of your documentation), but what it does after pressing 'Load' or 'Save' as a command is more involved. Quote Link to comment Share on other sites More sharing options...
+batari Posted March 21, 2012 Share Posted March 21, 2012 DPC+ is basically expanded DPC with coprocessor functions. Most games use the coprocessor which would require a full Thumb core on the FPGA. Quote Link to comment Share on other sites More sharing options...
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