colecovision 24k mod need detect ay-3-8910

[+5-11under]

... and only one of the RAM chips.

... the untested and somewhat incomplete PM, by the way.

[JamesD]

Check the datasheet at http://map.grauw.nl/resources/sound/generalinstrument_ay-3-8910.pdf

 

BDIR=0 BC2=1 BC1=0 must be generated by default (inactive chip, that is not accessed)

BDIR=0 BC2=1 BC1=1 must be generated by port 52H

BDIR=1 BC2=1 BC1=0 must be generated by port 51H

BDIR=1 BC2=1 BC1=1 must be generated by port 50H

 

So go ahead and make decoding logic that generates these signals

 

Note that in datasheet you can see there are three possible BDIR/BC2/BC1 combinations for inactive chip, choose the best one to reduce logic use.

 

For decoding you'll need only IORQ, A7-A4 and A1-A0.

BC2 is always 1 and could be tied to +5v.

That means you only need to generate BDIR and BC1.

BDIR=0 BC1=0 must be generated by default (inactive chip, that is not accessed)

BDIR=0 BC1=1 must be generated by port 52H

BDIR=1 BC1=0 must be generated by port 51H

BDIR=1 BC1=1 must be generated by port 50H

 

The following could be wrong so you'd want to verify it but...

 

The smallest way to do this would be a PAL or GAL capable of at least 10 inputs and 2 outputs.

 

Valid Address logic (50h - 52h) during IO request:

VA = ! IORQ * A7 * A5 * !(A6 + A4 + A3 + A2) * !(A1 * A0)

 

AY control logic:

BDIR = VA * RD

BC1 = VA * !A0

At least if RD logic works like I think it does which would be active (ow) during IORQ read and inactive (high) during IORQ write.

 

If I could get my device programmer software to work with my current OS I'd burn you a GAL.

 

*edit*

I haven't written PAL ASM in quite a while so I make no promises that's written correctly.

BTW, I think 50H would actually be read/write and 52H wouldn't really be needed. Why they used another port I don't know. Perhaps MSX does.

Edited November 8, 2013 by JamesD

[chart45]

i take help from all of you and everything that someone can teach me ill take it thanks

[JamesD]

This will help you read the logic from the PAL ASM. GAL ASM is pretty much the same for what I used.
Jump to page 15 to see how to read the operators.

http://www.taskit.de/fileadmin/taskit/download/manuals/GAL-ASM-Starterkit_Manual.pdf

[JamesD]

BC2 is always 1 and could be tied to +5v.

That means you only need to generate BDIR and BC1.

BDIR=0 BC1=0 must be generated by default (inactive chip, that is not accessed)

BDIR=0 BC1=1 must be generated by port 52H

BDIR=1 BC1=0 must be generated by port 51H

BDIR=1 BC1=1 must be generated by port 50H

 

The following could be wrong so you'd want to verify it but...

 

The smallest way to do this would be a PAL or GAL capable of at least 10 inputs and 2 outputs.

 

Valid Address logic (50h - 52h) during IO request:

VA = ! IORQ * A7 * A5 * !(A6 + A4 + A3 + A2) * !(A1 * A0)

 

AY control logic:

BDIR = VA * RD

BC1 = VA * !A0

At least if RD logic works like I think it does which would be active (ow) during IORQ read and inactive (high) during IORQ write.

 

If I could get my device programmer software to work with my current OS I'd burn you a GAL.

 

*edit*

I haven't written PAL ASM in quite a while so I make no promises that's written correctly.

BTW, I think 50H would actually be read/write and 52H wouldn't really be needed. Why they used another port I don't know. Perhaps MSX does.

I *think* BDIR should actually be:

 

BDIR = VA * !A1