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68020 card for Mega STE (and later for STE/STF)


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Both

 

Nice. Does that mean Atari Corp was experimenting with both CPUs in-house at the time? Most of us knew Atari was considering the 020 for the TT until Commodore beat them to the punch with an 020 model and then Atari Corp staff started claiming they were disappointed with the 020 - even though it had been on the market since 1984 and there shouldn't have been any negative surprises for them to discover - and were going to skip it and move onto the 030 instead. Sig Hartmann used to speak ill of the 020 in interviews and at user's group meetings.

 

I think I can say most of us ST owners back then would've liked the STE to have been released with an 010 or an 020 and VGA graphics. :)

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Nice progress!!!! Can't wait for a finished project!!! Hope it dose not fall victim to the "last 10% failure" where builders lose interest and a good/great project becomes abandon-ware. I've lost count of these.

 

What do you project to MSRP to be? I have several STE's waiting..

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@LynxPro : I too think atari had done some test with the 68020 either in the TT or a new version of the MegaSTE (the MegaSTE was released after the TT as far as I can remember).

 

@Klund1 : No idea yet. The CPLD if fairly cheap (~ $7 for an ATF1504AS PLCC 44), the test board were $85.20 for 3, so $28.40 each (4 layers). The price of a 68020RC33, depending on what you can find on eBay.. about $30. Then there is that damn PLCC 68 plug.. that's the most expensive part.. They are about $39 a piece (plus shipping and taxes). On the dev board I also put an expansion connector (DIN 41612) with all the 68020 signals .. $11, add resistors, caps, headers, oscillator.. that gives a build cost of about $120 so far including the CPU. The board can probably be made for a lot cheaper once I've solve everything and it's working.

 

Right know .. I know the CPU boots, I see a lot of TOS access, I see ACIa access but it crashes after a while and I never get the white screen with the Atari logo.

I know that my /AS, /UDS, /LDS signals are fine. I'm fairly sure that my VMA and E signal are also fine as they match what I can see with the 68000.

DSACK 1 is definitely working (it tracks DTACK) as the TOS access work. DSACK0 (for ACIA access on 8 bit) during VMA access seem to also work.

I know I have a weird issue as the /BG pin coming from the mother bord seem to follow DTACK .. it shouldn't as this is an output pin on the 68000/68020 .. so the issue might be there..

As I haven't seen any logic analyser trace fo a 68020 on an Atari I'm a little bit in the dark. I don't mind sharing all my equations for the CPLD as at this stage it's mostly coming from the Motorola AN944, the LUCAS code and some other code I found left and right. As I have to use WinCUPL for the CPLD, I have to adapt the code I find and there is always a chance of me messing up something.

I do intend to finish the project as I want a 68020 in my MegaSTE... as for how long that will take.. no idea.

I'm going to assemble a 2nd card to see if I see the same issue on /BG. I also need to order more PLCC 68 plug as well as a few ATF1502 and ATF1504 (same pinout, more MLC in the later so that I can experiment with more stuff than needed and I can trim down later) for the 2nd board (and the 3rd one at some point as I have 3 PCB).

The challenge is always being the only dev on something like this. As I do this to learn I'm bound to make error.. and without any input from a team mate this takes a lot more time to get sorted out.

 

Rodolphe

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Wait… TOS 2.06 natively supports which CPU, the 68010 or the 68020?

Why should it support 68020 which fits not in Mega STE ?

But when we talk about all it: TOS in TT, so 3.06 is very similar with 2.06 . There is PMMU support, support for extra video modes. Desktop self is almost identical.

I don't think that Atari went 68030 just from some commercial/propaganda reasons. PMMU can do some really useful things.

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  • 2 weeks later...

What TOS 2.06 supports is a fix for the "move SR, <EA>" instruction that is a user instruction on the 68000 but a supervisor instruction on the 68010 (and up).

Also, I have finally received the 2 PLCC68 plug so I can assemble the 2 other board... hopefully this weekend.. if not.. next weekend.

Rodolphe
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Due to the support for virtual memory, the stack was also different when interrupts were triggered.

 

I'm really wishing I hadn't given away all my ST stuff a few years back, as I looked into this back in the early 90's after seeing that same AN (which I still have). I did spend a lot of time investigating this. Perhaps you could send me your logic equations and I'll see if I notice anything. Reading your descriptions of DSACK0/1 reminds me that there was a problem with byte access, as the 68000 just used the upper or lower 8 bits, but the 68020 always did 16 bits and I though you had to shift which way the byte went?

 

Time to pull out my books!

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@MrMartian.

I can send you the equations as well as the Eagle files.

For 8 bit access, the 68020 expect a 8bit device to be wired on D24-D31 (which is D8-D15 of the 68000 bus) and /DSACK0 is used to terminate the cycle.

I'll pm you my email so we can talk about this.

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Well ... that would not be as fun as making my own ;)

Plus I'm not sure we can still find them and even less sure they fit in a MegaSTE :)

I spent about 6-7 hours yesterday trying to debug all of this with MrMartian.

We changed the DSACK0 on ACIA access to DSACK1 for all access and that seems to work.

BG seem to behave now. I cleaned the 68000 PLCC socket as there was a little bit of corrosion and bent back the pin toward the inside to get a better contact on the PLCC plug. We can see the 68020 starting, TOS access are fine as we can see proper cycle in 4 clock cycle and DSACK1 asserted at the right time. ACIA access looked better at the end of the day (with LDS and UDS at the right level).

We still see some weird pulses on some signals (like I saw on BG before) and I think it might be a bug in the logic analyzer software that shows a HI level for

a 0.1V signal. Of course if the analog sampling is to slow I might not see a spike (I use a Logic 16 from Saleae).

So it still doesn't work but I think we're making progress.

 

Rodolphe

Edited by rpineau
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  • 2 weeks later...

So before assembling the other board I'm going to spend a little bit more time on the current one as the issues I see (see http://www.exxoshost.co.uk/atari/last/020BOOSTER/update) might require a new board to fix them.

I might also try to find a STE and put a TOS 2.06 on it for testing as the MegaSTE might behave differently in term of signal quality.
Rodolphe
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  • 2 weeks later...

I am glad you are doing this for the Atari community and I extend my kudos to you. I have a question, though. You said this 68020 upgrade will work with STF and STE. Now, I have a 520STFM and a 1040STE. I understand that these are lower end STs. Will your upgrade card work on these computers as well? I only ask because I am understandably curious. Thanks for your attention. :)

Edited by jericho_21
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This card will plug in place of the CPU. So from a hardware standpoint there's going to be 2 (or 3) version : STF, STE (and may be a specific version for MegaSTE as it has a native 8/16 MHz bus).

The main issue for some people will be the space in the machine depending on the mother board revision.

Also, you'll need a TOS 2.06 in the machine (people have asked that I don't put a TOS on the board and allow people to do their own TOS 2.06).

Right now the card still doesn't work (there is progress.. but still).

I didn't have time to work on this for the last 2 weeks so no news on that front.

The goal is of course to make it works on as many machine as possible but some motherboard will simply not have the space (specially the one with the STF with CPU close to the floppy). Now depending on the demand I might be able to produce multiple layout and may be do different STF versions.

But I first need to focus on getting the logic working first.

Once I get a full boot to TOS, then we can look at different layout and optimisations.

 

Rodolphe

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Have you tried this as a source of 68020?

 

http://www.tekmos.com/products/68020-microprocessors

 

 

Is there any thing that can be done to help? have you considered crowd funding or even donations toward development?

 

Barnie

 

 

 

@LynxPro : I too think atari had done some test with the 68020 either in the TT or a new version of the MegaSTE (the MegaSTE was released after the TT as far as I can remember).

 

@Klund1 : No idea yet. The CPLD if fairly cheap (~ $7 for an ATF1504AS PLCC 44), the test board were $85.20 for 3, so $28.40 each (4 layers). The price of a 68020RC33, depending on what you can find on eBay.. about $30. Then there is that damn PLCC 68 plug.. that's the most expensive part.. They are about $39 a piece (plus shipping and taxes). On the dev board I also put an expansion connector (DIN 41612) with all the 68020 signals .. $11, add resistors, caps, headers, oscillator.. that gives a build cost of about $120 so far including the CPU. The board can probably be made for a lot cheaper once I've solve everything and it's working.


 

 

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I did contact Tekmos .. they never replied.

Right now the issue is not funding. I need to figure out why it crash at some point in the boot.

What can be done to help ... well .. I would need someone that is better than me at CPLD (not hard to find ;) ), that can work in WinCUPL, can buy the Atmel JTAG programmer .. on my side I would provide a fully populated card for free.

Currently I only have the STE/MegaSTE version (with a 68000 PLCC socket). It also requires a TOS 2.06 (for 68020) support.

Whoever is interested probably also need a small logic analyser.

Rodolphe

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Maybe Tekmos have a reseller, I do find it short sighted that these companies don't make some effort to allow easy access to their products. If someone is making using of their parts in a spare time project its possible they may be in a fulltime job that has similar requirements :)

 

What about putting the project files on github or similar? would that be possible?

 

I did contact Tekmos .. they never replied.

Right now the issue is not funding. I need to figure out why it crash at some point in the boot.

What can be done to help ... well .. I would need someone that is better than me at CPLD (not hard to find ;) ), that can work in WinCUPL, can buy the Atmel JTAG programmer .. on my side I would provide a fully populated card for free.

Currently I only have the STE/MegaSTE version (with a 68000 PLCC socket). It also requires a TOS 2.06 (for 68020) support.

Whoever is interested probably also need a small logic analyser.

Rodolphe

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Tekmos is making 68020 cpu mostly for 1 reason .. the US Military.

So they might not care about small order like we would need for this card.

I can share the files.. no need for github.. just ask.

The current files for the CPLD have no magic trick in there so sharing them is no issue :)

I can also share the Eagle schematics and PCB of the prototype (useful for debugging).

 

Rodolphe

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  • 4 weeks later...

Quick update :

I have been very busy with work and other project in the last 4 weeks so the only thing I manage to do is to build a 2nd card and send it to someone who contacted me and want to help (he got all the tools needed for this). I added a pull-up on A0 (was missing) and on the CPU /BG. I also added 2 electrolytic capacitor (33uF each) on the 5V line.
I haven't yet tested this to see if it helps with the weird things we were seeing on some signals.
You can also blame the Rugby world cup for my lack of time spent on this :)
Rodolphe
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  • 3 weeks later...
  • 3 weeks later...

Today we had a breakthrough.

Even though we still see some issues with the Atmel ATF series (issues with the output enabled of some output when using combinatory equation for these) we got a working proto. All of this thanks to Juliusz who found most of the problem I had (mostly related to the OE issue).
He was able to get it working on a STE with TOS 2.06.
Here are a few perf he got from Gembench running the 68020 at 8MHz:
========================================
Results (I had blitter on, reference is STE with blitter):
Display 95%
CPU 164%
Average 113%
Integer: 284% !!
VDI graphics: 126%
RAM access: 131%
ROM access: 151%
All other are about 90-100%
With blitter off, reference: STE with blitter off:
Display 116%
CPU 165%
Average 129%
Integer div: 285%
VDI graphics: 132%
RAM: 131%
ROM: 152%
Blitting: 151%
All other slightly above 100%
Float: 93%
VDI Enquire: 91%
========================================
Now that we have a working version of the code (and a few hardware fixes to go with it) we can move forward and start trying the 33MHz switching on /AS (same as the 68000 booster from exxos).
Rodolphe & Juliusz
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Today we had a breakthrough.

Even though we still see some issues with the Atmel ATF series (issues with the output enabled of some output when using combinatory equation for these) we got a working proto. All of this thanks to Juliusz who found most of the problem I had (mostly related to the OE issue).
He was able to get it working on a STE with TOS 2.06.
Here are a few perf he got from Gembench running the 68020 at 8MHz:
========================================
Results (I had blitter on, reference is STE with blitter):
Display 95%
CPU 164%
Average 113%
Integer: 284% !!
VDI graphics: 126%
RAM access: 131%
ROM access: 151%
All other are about 90-100%
With blitter off, reference: STE with blitter off:
Display 116%
CPU 165%
Average 129%
Integer div: 285%
VDI graphics: 132%
RAM: 131%
ROM: 152%
Blitting: 151%
All other slightly above 100%
Float: 93%
VDI Enquire: 91%
========================================
Now that we have a working version of the code (and a few hardware fixes to go with it) we can move forward and start trying the 33MHz switching on /AS (same as the 68000 booster from exxos).
Rodolphe & Juliusz

 

Thanks for this good news. It is quite recent as well. I am finding this very interesting what you are trying to accomplish here. I am glad of your progress. Thanks again for everything. :)

Edited by jericho_21
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Juliusz started doing some testing with the 8/32 MHz switching (the end goal is to always be at 32MHz) with good results. He had to use the system 32MHz and not the 32MHz oscillator on the board as the switching between 2 unrelated clocks was causing issue. Here are some result at 8/32 MHz :

 

Blitter OFF :

GEM Bench v4.03             Ω Ofir Gal - 3 March 95
============================================
STE  TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Disabled
NVDI not present
Video Mode: 640*200*4
FPU not present
Run and Malloc from STRAM
Ref: STE, No Blitter, ST Medium
============================================
GEM Dialog Box:             6.685    118%
VDI Text:                  10.610    132%
VDI Text Effects:          18.110    133%
VDI Small Text:            11.080    122%
VDI Graphics:               9.085    208%
GEM Window:                 2.045    160%
Integer Division:           1.575   1142%
Float Math:                12.165    109%
RAM Access:                 3.020    208%
ROM Access:                 2.660    237%
Blitting:                   3.430    257%
VDI Scroll:                 7.145    188%
Justified Text:             9.235    149%
VDI Enquire:                2.615    101%
New Dialogs:                7.840    121%
============================================
Graphics:                            153%
CPU:                                 424%
Average:                             225%

Blitter ON :

GEM Bench v4.03             Ω Ofir Gal - 3 March 95
============================================
STE  TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Enabled
NVDI not present
Video Mode: 640*200*4
FPU not present
Run and Malloc from STRAM
Ref: STE + Blitter, ST Medium
============================================
GEM Dialog Box:             5.785     97%
VDI Text:                   5.855     98%
VDI Text Effects:          10.010    120%
VDI Small Text:             6.635     99%
VDI Graphics:               8.845    194%
GEM Window:                 1.580    100%
Integer Division:           1.570   1143%
Float Math:                12.145    109%
RAM Access:                 3.020    208%
ROM Access:                 2.610    241%
Blitting:                   1.350    102%
VDI Scroll:                 4.265    103%
Justified Text:             5.555    100%
VDI Enquire:                2.610    101%
New Dialogs:                7.445    103%
============================================
Graphics:                            110%
CPU:                                 425%
Average:                             194%

We think we might have some timing issue on /BR, /BG, /BGACK which might explain the "slow" blitter result (or may be we don't and Gembench timing loop are wrong on a 68020).

 

Rodolphe

Edited by rpineau
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