What if? Designing "Geneve 2020". Cool 3D views!

[Anthony Kristler]

this discussion is very insightful, I only have a question, when will this computer be available, i am a very die hard ti fan

[+FarmerPotato]

On 2/14/2024 at 7:31 AM, Anthony Kristler said:

this discussion is very insightful, I only have a question, when will this computer be available, i am a very die hard ti fan

Sorry, I'm not setting any ship dates. It's been my passion for the past four years...

 

 

 

[+FarmerPotato]

Update:

 

I was stuck finding shorts. 
 

First AD15 was shorted somewhere. Probably at the RAM. But so was VCC-GND.

 

I found it last night after desoldering the accused culprit RAM chip again.
 

The short was a solder whisker, on the farthest, unused RAM footprint. The pinout of this RAM is smart but tricky. To reduce switching noise, they put VCC and GND on the middle pins of each side. Which makes them easy to short. I lost a lot of time on the assumption that my RAM had some solder bridge underneath. 
 

 

I'm getting weary of build difficulties. With that short found, I find that my ROMs aren't working. It seems like the two PLCC sockets' springiness has worn out, at least on the side that has chip select and output enable. Weird that its  both. The signal reads perfectly AT the socket, it just doesn't reach the chip pin. (I poked a wire in because the probe tip is too wide.) 

Either I managed to wear out both PLCC sockets at once, or the chips have some weird damage. But I was able to read, rewrite and verify them on the T56 last night. 
 

[+TheBF]

I miss DIP sockets...  

[+FarmerPotato]

15 hours ago, TheBF said:

I miss DIP sockets...  

Seriously considering DIP again for the EEPROM.  When I replace the LS612 memory mapper (DIP-40) there will be room.  And it will simplify the address/data bus route. 

 

--

 

The PLCC-32 sockets were Amphenol brand, fresh from Mouser.  At least 10 insertion cycles so far. 

 

Anyone have advice here?  How to keep PLCC sockets in working order?

(and why would both fail in the same remove/insert cycle?)

 

 

 

[RickyDean]

2 hours ago, FarmerPotato said:

Seriously considering DIP again for the EEPROM.  When I replace the LS612 memory mapper (DIP-40) there will be room.  And it will simplify the address/data bus route. 

 

--

 

The PLCC-32 sockets were Amphenol brand, fresh from Mouser.  At least 10 insertion cycles so far. 

 

Anyone have advice here?  How to keep PLCC sockets in working order?

(and why would both fail in the same remove/insert cycle?)

 

 

 

You can get PLCC 32 sockets that are through hole like these https://www.digikey.com/en/products/detail/amphenol-icc-(fci)/54020-32030LF/4292083?utm_adgroup=General&utm_source=google&utm_medium=cpc&utm_campaign=PMax Shopping_Product_Zombie SKUs&utm_term=&utm_content=General&utm_id=go_cmp-17815035045_adg-_ad-__dev-c_ext-_prd-4292083_sig-Cj0KCQiAxOauBhCaARIsAEbUSQSWaLHTZZieX8zoV9g_ok1u392lSgyfMLlPwjjlA2zEBCxvKYioCJEaAuUTEALw_wcB&gad_source=1&gclid=Cj0KCQiAxOauBhCaARIsAEbUSQSWaLHTZZieX8zoV9g_ok1u392lSgyfMLlPwjjlA2zEBCxvKYioCJEaAuUTEALw_wcB

 

Would that help? These are similar to the ones I used on my Ubergrom builds.

Edited February 24 by RickyDean
spelling, added content

[+FarmerPotato]

1 hour ago, RickyDean said:

Would that help? These are similar to the ones I used on my Ubergrom builds.

I do have those. The surface mount kind, I found, are easier to route. 
 

it's not the PCB to socket, it's the socket to chip that's no  longer making contact. 

[RickyDean]

21 minutes ago, FarmerPotato said:

I do have those. The surface mount kind, I found, are easier to route. 
 

it's not the PCB to socket, it's the socket to chip that's no  longer making contact. 

Ok, that's a bit wierd. You aren't using a pointed device to remove the plcc chip from the socket and maybe bending back the pins are you?

[+Ksarul]

I've never had any socket issues with PLCC stuff once I got them seated properly on the board. I have had problems getting them to program in a normal PLCC socket, but once I switched to the flap-style live bug sockets for programming, that problem disappeared too. I haven't had issues with the dead-bug box-style sockets for programming either, but I personally prefer the flap style when programming a bunch of chips.

 

The only thing I could think of that might damage the regular sockets is too much asymmetrical stress on the contacts that make a few of them lose their grip on the chip. Probably near the insertion notches.

[Tornadoboy]

This maybe a stupid question but is there such a thing as a PLCC ZIF (Zero Insertion Force) socket? If so maybe you'd have better luck with those during the proto stage given the repeated removals, then just go with normal sockets once you've settled on the design. 

Edited February 25 by Tornadoboy

[+FarmerPotato]

@Ksarul  Um what do you mean by dead bug, flap, live bug in PLCC? 
 

In the prior board, I used  ZIF DIP sockets (lever) happily. Might go back. At one point I drew two Memory Mezzanine daughter boards, one using DIP. 
 

Amphenol says the PLCC socket life is  25 insertions. My problems are at the short end of PLCC-32 (sides are 7,9,7,9 pins).
 

But then, on microscope  I can't see any gap.

 

I tried two new chips, same problem. 
 

But on one try, I got out 00 instead of Ff when 

I poked two tiny wires into both RD and CE.  Expected 80. (So maybe still got AD15 shorted.)

 

Chips are SST 39SF010 (128K x 8 ) PLCC. 

Guess I'm going to have to swap in new sockets. Again. 

 

[+Ksarul]

Here is an example of the 32-pin flap style test and burn-in sockets. These are always in live-bug configuration (chip is placed top side up in them).

 

Here is an example of the 32-pin square test and burn in sockets. These can show up in live bug or dead bug style (dead bug has the chip placed upside down in the socket).

 

Both types can be obtained without the DIP adapters they are soldered into for use with programmers. I have a couple of each type loose, as one of my programmers expects the bare PLCC sockets in its programming slots (ADVIN gang programmer for PLCC chips).

 

Pomona also makes some really nice plug sockets for the various PLCC chips that give you test points at the top for every pin, but they can be a bit pricey. The 32-pin also only seems to show up in the kits with everything from 20 to 84 pin adapters as well, making them even worse on pricing.

[+FarmerPotato]

On 2/24/2024 at 1:39 PM, RickyDean said:

Ok, that's a bit wierd. You aren't using a pointed device to remove the plcc chip from the socket and maybe bending back the pins are you?

I'm using the puller that came in the XGecu kit. Goes under the corners. 
 

I have damaged chips taking them out. 

[+FarmerPotato]

So I took out the sockets. Put in the last two I have. New chips. Very easy to insert. But still no good. 
 

I also replaced the bridge to the logic analyzer. The DuPont crimps are wearing out and I guess that's why I get so many tiny glitches. 

 

Problem is continuity between the address latch and ROM. Address lines L_A10, 11 are bad. They read solid 0 or 1 at the origin, but wobbly at the ROM. I traced L_A12 as a control. 
 

So likely the ROM was not the problem all along. The floating input could result in the address pointing into all FF. 

The L_A10 and 11 traces have continuity between the two ROMs. I've deduced that the break is a damaged via.  Under the brand new plastic socket.  

I'm stuffing the via with tinned bodge wire. 

 

 

[RickyDean]

36 minutes ago, FarmerPotato said:

So I took out the sockets. Put in the last two I have. New chips. Very easy to insert. But still no good. 
 

I also replaced the bridge to the logic analyzer. The DuPont crimps are wearing out and I guess that's why I get so many tiny glitches. 

 

Problem is continuity between the address latch and ROM. Address lines L_A10, 11 are bad. They read solid 0 or 1 at the origin, but wobbly at the ROM. I traced L_A12 as a control. 
 

So likely the ROM was not the problem all along. The floating input could result in the address pointing into all FF. 

The L_A10 and 11 traces have continuity between the two ROMs. I've deduced that the break is a damaged via.  Under the brand new plastic socket.  

I'm stuffing the via with tinned bodge wire. 

 

 

Understood, don't get frustrated, stay cool and you'll get there. Those little gremlins kick us all at some point or another.

[+FarmerPotato]

Two bugs fixed, one new one. 
 

Via repair was successful. I'm not sure it was the problem though. Continuity measurement was unreliable!  

 

At U3 , the address latch, those outputs for L_A10,11 had poor solder joints.

 

They sometimes conducted when I put pressure on the pin from on top, but not when probing the vias.

 

Similar bug  is L_A3 is shorted somewhere.  I can deduce the addresses that data really came from. 

 

Worst case, L_A4 is shorted to L_A3 underneath the ROM sockets I just replaced.

 

My construction skills are still short of what I'm trying to build. It could be the amount of solder paste. 

 

I imagine little solder paste stencils for 1-chip footprints. With local registration holes. 
 

 

 

 

 

[+FarmerPotato]

No breakthrough.  

 

In layout, I made a terrible mistake:  a LA_3 via is next to a ground pad.  I removed the solder blob, but it still shows as shorted.  I had to bend back the ground pin of the LS259B:

 

 

The vias under the LS259B are to get L_A1, L_A2 and L_A3 into the chip.  It's very cramped at the edge of the board--lesson learned. 

 

 

[+dhe]

Any updates FPo?