Questions about reading TIA schematics

[Smidge]

I need help understanding how to read the TIA schematics, specifically the schematic for the audio circuitry (sheet 4 here). I'm struggling with some of the notation. My goal is to add audio support to my 2600 emulator, Tamera, by first recreating the audio logic in something like BOOLR so I can figure out how the cryptically named modes of AUDCx work (like wtf does "5-bit poly to 4-bit poly" mean).

 

Question 1: What does the circle over intersecting lines mean?

This notation appears all over the place. Here's an example:

 

Someone asked this a few years ago on Reddit and actually got a response from someone claiming to have worked on the 7800 at General Computer Company in the 80s. According to that person, the circled intersection represents a wired AND-gate as described here, with the "resistor to nowhere" being a pull-up resistor (effectively a hard-wired 1 to the wired AND-gate I think). Is it correct that these are just AND-logic?

 

Question 2: What are the dual outputs of the audio control registers?

Each bit of the audio control register (AUDCx) feeds into a black box with two outputs:

Black boxes such as these appear throughout the TIA schematics whenever a logical unit is replicated, and they are typically accompanied by a separate schematic off to the side. Examples can be found on the same schematic sheet as the audio circuit for the player graphics registers and the audio frequency registers. However there is no such explicit schematic for the audio control register. There is a similar sub-unit for the audio frequency circuit (1 input per bit with two outputs), but it is not clear whether it is the same sub-unit used for the audio control registers.

 

Question 3: What are these, transistors?

I'm referring to the two similar looking symbols that bump up and have a line over top. Are they transistors acting as switches here? Why does one have an asterisk? How can I tell if the switch is active low or high?

 

Question 4: Why does this NOR-gate have wings?

Do the extra bits that stick out on the sides have any special meaning or is it just to add room for more inputs?

 

Question 5: Are the "5-bit poly" and "4-bit poly" circuits shown explicitly as separate units?

The TIA documentation mentions the audio circuit uses a 9-bit shift register which does not appear to be in the schematic. However there is what looks to be a 5-bit polynomial shift register (the five D1 boxes under "AUDIO NOISE GEN.") and another 4-bit polynomial shift register on the bottom right (implemented with SR-latches). (The 5-bit feeds into the 4-bit which I suppose gives 9 bits). Are these two units the "5-bit poly" and "4-bit poly" which are mentioned in the documentation for the AUDCx registers?

[stepho]

No-one else answered, so I'll give it a shot - even though my hardware skills are a bit on the vague side.

 

Q1

Lines that cross with no circles do not touch each other. Some designers used a loop that look a bit like a bridge for the same thing.
Lines that cross with circles are a physical connection.
At the bottom of the vertical lines there are resistors and at the left of the horizontal line there is another resistor.
These connections and resistors form a wired AND (or perhaps a wired OR - my brain is a bit fuzzy at the moment).

 

Q2
The AUC0/1 registers are made from flip-flops.
These flip flops had both 0 and 1 outputs - of which exactly 1 would be active at any given time.
The 2 outputs are the 0 and 1 outputs of each flip-flop.
 

Q3

Yes, they are transistors.
When the centre connection is active then the left and right legs are effectively connected together.
They act pretty much like relays do (gross simplification).
See https://en.wikipedia.org/wiki/MOSFET

 

Q4

Hand drawn circuits like this were made using a plastic template sheet with lots of standard component shape cut out of it.
The designer would place the cut out over the work, stick his pen in and run it around the hole.
If you needed more inputs than would fit on the standard shape then you added wings.
The exact form of the wings was more of an individual style thing.

 

Q5

I agree with you that on sheet 4 of 5 a 5-bit "AUDIO NOISE GEN." polynomial feeds into an unnamed 4-bit polynomial counter.
Your assumption seems reasonable to me but I'm further out of my comfort zone here.

[Smidge]

Thanks for the reply! Given that the circled connection represent either wired-AND or wired-OR logic and that the output of the AUDC registers are just the AUDC bits and their complements, I think I am still not reading the schematic correctly. Here is the audio bus with inputs and outputs labeled:

• D0-D3 are the AUDCx bits
• A prime ' indicates the complement (D2' = complement of D2)
• P0-P3 are the inputs from the polynomial counter
• Q0-Q4 are the outputs of the vertical lines (inputs to the top horizontal line)
• S is the output of the top horizontal line

The way I read this, assuming the circled connections represent AND logic, is:

• S = Q0 & Q1 & Q2 & Q3 & Q4
• Q0 = D0 & D1 & D2 & D3
• Q1 = P0 & D2 & D3
• Q2 = P1 & D2' & D3'
• Q3 = P2 & D2' & D3
• Q4 = P3 & D2 & D3'

This doesn't seem right since S could never be 1. For S to be 1, all of the Qx must be 1. In order for Q0 to be 1, all of the Dx must be 1. But if all of the Dx are 1, then D2' = D3' = 0, and then Q2 = Q3 = Q4 = 0, and it must be that S = 0. The same issue appears if the circled connections are OR logic, but S would always be 1 and could never be 0. Where am I going wrong?

[ChildOfCv]

On 12/5/2021 at 9:00 PM, Smidge said:

I need help understanding how to read the TIA schematics, specifically the schematic for the audio circuitry (sheet 4 here). I'm struggling with some of the notation. My goal is to add audio support to my 2600 emulator, Tamera, by first recreating the audio logic in something like BOOLR so I can figure out how the cryptically named modes of AUDCx work (like wtf does "5-bit poly to 4-bit poly" mean).

 

Question 1: What does the circle over intersecting lines mean?

This notation appears all over the place. Here's an example:

 

It's shorthand for a decoding circuit.  When you find mass x-bit to y-function translation, it will often be presented this way, to tell you that for function y, these x bits must be active.  You'll see the same thing in the 650x instruction decoding circuit schematics.  This is a bit more interesting though because it seems that all 5 of those lines have driven bits coming in from both the register and from the shift feedback.  It has only two outputs.  The first is the leftmost one.  It's probably only dependent on the driven elements of that leftmost one.  The second is the sum of the 5 lines and goes into the 4-bit shift register.

 

Quote

Question 2: What are the dual outputs of the audio control registers?

Each bit of the audio control register (AUDCx) feeds into a black box with two outputs:

Black boxes such as these appear throughout the TIA schematics whenever a logical unit is replicated, and they are typically accompanied by a separate schematic off to the side. Examples can be found on the same schematic sheet as the audio circuit for the player graphics registers and the audio frequency registers. However there is no such explicit schematic for the audio control register. There is a similar sub-unit for the audio frequency circuit (1 input per bit with two outputs), but it is not clear whether it is the same sub-unit used for the audio control registers.

It appears that all inputs are latched using the simple latch circuit on several other pages, as well as the left part of the circuit shown on this page.  It is unfortunate that they didn't call it out explicitly, but everything checks out on it being the same thing (such as the inverter and non-inverter to clock the latch).

 

Quote

 

Question 3: What are these, transistors?

I'm referring to the two similar looking symbols that bump up and have a line over top. Are they transistors acting as switches here? Why does one have an asterisk? How can I tell if the switch is active low or high?

Yeah those are MOSFETs that act as switches.  The asterisk may indicate intended current flow directions.  In this case, the upper resistor provides the signal when clocked, then the lower transistor maintains it when not clocked by feeding the output of the inverter-inverter back to it.

 

Quote

 

Question 4: Why does this NOR-gate have wings?

Do the extra bits that stick out on the sides have any special meaning or is it just to add room for more inputs?

More inputs.  It seems to be a stylistic choice.  Some schematics just pack the inputs into the curved area, others like this one add wings.

 

Quote

 

Question 5: Are the "5-bit poly" and "4-bit poly" circuits shown explicitly as separate units?

The TIA documentation mentions the audio circuit uses a 9-bit shift register which does not appear to be in the schematic. However there is what looks to be a 5-bit polynomial shift register (the five D1 boxes under "AUDIO NOISE GEN.") and another 4-bit polynomial shift register on the bottom right (implemented with SR-latches). (The 5-bit feeds into the 4-bit which I suppose gives 9 bits). Are these two units the "5-bit poly" and "4-bit poly" which are mentioned in the documentation for the AUDCx registers?

It looks like the 5-bit and 4-bit are mostly independent.  But the output of the 5-bit feeds into the 5th decoder line which helps to decide the input to the 4-bit, so depending on how the registers are programmed and on the feedback state of the 4-bit register, it will take the output of the 5-bit into consideration and make a combined 9-bit register.  Consultation of the TIA technical manual would probably make it more clear when you match up what it says programming various bits does, to how the circuit would have to accomplish it.

Edited December 10, 2021 by ChildOfCv

[ChildOfCv]

I created a sim of the entire audio circuit in Logisim.  I used the open-collector and transistor setup for the decoder grid.  You can see how the 2 upper bits of the AUDC register control the 4-bit register's feedback source while the lower 2 control the 5-bit register.

 

Sound.zip

[Smidge]

12 hours ago, ChildOfCv said:

I created a sim of the entire audio circuit in Logisim.  I used the open-collector and transistor setup for the decoder grid.  You can see how the 2 upper bits of the AUDC register control the 4-bit register's feedback source while the lower 2 control the 5-bit register.

 

Sound.zip 4.77 kB · 2 downloads

That's awesome, thank you! Seeing the decoders wired up as you show them makes so much more sense. I see now that they're effectively doing NOR logic rather than AND or OR which does allow the output of that bus to be not just a constant 1 or 0. I've been playing around with the simulation for about an hour now, and I do have a few questions about how you implemented it if you don't mind.

 

Q1. How did you know to implement each "D1" latch in the 5-bit poly as two connected D flip-flops?

For reference, this is the first D1 cell from the schematics:

and from the simulation:

 

Q2. What's up with this AND gate that doesn't do anything?

This AND gate feeds back into the SR-latches in the 4-bit poly (I think the clock line for the latches?). By the design of the inputs it's always low. In the schematic this part looks like this:

and to be honest I don't know what's going on with the lower inverter that has that extra line coming into it. The "E" indicates this part was added in a later chip revision; so did they for some reason just permanently disable this output?

 

Q3. Why are these two transistor simulated with flip-flops instead of transistors?

[ChildOfCv]

7 hours ago, Smidge said:

That's awesome, thank you! Seeing the decoders wired up as you show them makes so much more sense. I see now that they're effectively doing NOR logic rather than AND or OR which does allow the output of that bus to be not just a constant 1 or 0. I've been playing around with the simulation for about an hour now, and I do have a few questions about how you implemented it if you don't mind.

 

Q1. How did you know to implement each "D1" latch in the 5-bit poly as two connected D flip-flops?

For reference, this is the first D1 cell from the schematics:

and from the simulation:

 

They showed D1 on sheet 1.  It's a transistor to an inverter to another transistor to another inverter.  It's not quite a latch, but instead relies on parasitic capacitance and clock speed to hold its values.  I don't think Logisim simulates transistors in that sense very well, especially since it doesn't let you choose high clock speeds, so I used two inverting latches instead, each clocked by the opposing clock phase.

 

7 hours ago, Smidge said:

 

Q2. What's up with this AND gate that doesn't do anything?

This AND gate feeds back into the SR-latches in the 4-bit poly (I think the clock line for the latches?). By the design of the inputs it's always low. In the schematic this part looks like this:

and to be honest I don't know what's going on with the lower inverter that has that extra line coming into it. The "E" indicates this part was added in a later chip revision; so did they for some reason just permanently disable this output?

It takes advantage of propagation delay to only pulse the clock.  My suspicion is that the SR latches of the 4-bit are level-triggered.  It would certainly be simpler to implement, but it means the clock pulse must be extremely small, basically just enough to make the gate flip before the signal bleeds through.

 

7 hours ago, Smidge said:

 

Q3. Why are these two transistor simulated with flip-flops instead of transistors?

Same reason as above for the flip-flops.  I think they are intended to use capacitance to hold their last value after activation, but Logisim doesn't simulate that aspect of it.  So instead I used an active latch.

[Smidge]

I've finished my analysis of the output of the TIA audio circuit simulation provided by ChildOfCv and thought I'd share the results for others to reference in the future. My goal was to obtain the waveforms produced by each setting of the AUDC registers, which can be found below.

 

How I obtained the waveforms:

I used the logging feature of Logisim to record the output of the audio circuit for each clock. I ran the simulation at a high frequency (1 kHz) for about 10 seconds to make sure the waveform would repeat several times. I did this for each of the 16 possible values of AUDC. I then wrote a Python script to find the shortest repeating pattern of 0s and 1s for each waveform.

 

How to read the waveforms:

• The simulation encapsulates the audio control circuit (AUDC registers) of the TIA audio circuitry, which is positioned between the frequency divider (AUDF registers) and the volume adjustment (AUDV registers). Therefore the waveforms shown below do not include the effects of frequency division (effectively AUDF = 0, no division) or volume control (effectively AUDV = 1111, max volume). Each bit of a waveform is the output of the audio control circuit after receiving a clock signal.
• The output is either low (0) or high (1).
• The waveforms are the shortest repeating pattern of 0s and 1s. The period length is the number of 0s and 1s in the pattern.
• The waveforms all start with the longest sequence of 0s in the pattern. It just came out this way because of how I wrote the Python script.
• The AUDC values are shown in binary as D3 D2 D1 D0

Other notes:

• I trust the output of the simulation. I put the waveforms into my emulator and so far everything sounds like I would expect. However I doubt the games I've tested so far cover all of the possible AUDC values. I do get some occasional crackling but that's likely a problem with my implementation and not the simulation.
• AUDC = 0000, which is described as "set to 1", sets the output to 0. Could be this means all the 0s and 1s are flipped (not that it really matters).
• If there's anything I'm suspicious of it's the "set last 4 bits to 1" mode (AUDC = 1011) since all I got was 0s. It seems then to behave identically to the "set to 1" mode (AUDC = 0000).

 

TIA Audio Waveforms

AUDC = 0000 (set to 1), period length = 1
0

 

AUDC = 0001 (4-bit poly), period length = 15
000011101100101

 

AUDC = 0010 (div 15 -> 4-bit poly), period length = 465
000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111100000000000000000011111111111111111111111111111110000000000000000000000000000000111111111111100000000000000000011111111111110000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111111111111111111111110000000000000111111111111111111111111111111100000000000000000000000000000001111111111111111110000000000000111111111111111111

 

AUDC = 0011 (5-bit poly -> 4-bit poly), period length = 465
000000000000111110110000011010000000000001111110110000010010000000000111111000110011110110000001111111111011110010000100000011111111110011110010111100000111111111000111000010100000000111110000011111000010100000000111100111111110001110100000001111001111111000001000100000001111011110000000011011100001111111011100000001110010000001111110011000011111000110000001111110111000110000011100000001110000111001100111110000000001110111110001001100000000000111110111110001011

 

AUDC = 0100 and 0101 (div 2: pure tone), period length = 2
01

 

AUDC = 0110 and 1010 (div 31: pure tone), period length = 31
0000000000000111111111111111111

 

AUDC = 0111 (5-bit poly -> div 2), period length = 31
0000100101100111110001101110101

 

AUDC = 1000 (9-bit poly (white noise)), period length = 511
0000000001111100001000001110100011001101111101101011000100101110000110000011001001110101011011100011100100101010001110110011101110111111110111101110011110110001101010100111100100001011001000110111010111101010010110000001001101101101001000000110110010101100110011111110011100110101110010110100000001011101001110001010011010011000011100000100010111110010100100100010011111010010100000101010101111110101101010000110100010001111110001100010110110000101000101011101101111001100011110100001001001100101111000100001111

 

AUDC = 1001 (5-bit poly), period length = 31
0000011100100010101111011010011

 

AUDC = 1011 (set last 4 bits to 1), period length = 1
0

 

AUDC = 1100 and 1101 (div 6: pure tone), period length = 6
000111

 

AUDC = 1110 (div 93: pure tone), period length = 93
000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111

 

AUDC = 1111 (5-bit poly div 6), period length = 93
000000000011111100011111100001111111110000001111100000011110000011111111110000011100000001111

[SeaGtGruff]

I know this is a very late reply, but I saw this thresd and wanted to add a little to it since I spent some time several years ago trying to understand the TIA schematics and constructing an Excel spreadsheet to simulate the circuitry.

 

Those asterisks are-- I believe-- the places where you have a signal feeding backward (or looping back) into a circuit, such that the state of the whatsit will be indeterminate or random when you first start feeding power into the TIA. That might be incorrect, but the reason I believe that that's what it means is because you see those asterisks throughout the schematics and they always occur at places where a signal from further down the line is being brought back to form a loop.

 

When I was making my spreadsheet, each row represented a moment in time, and each column represented a transistor or gate or other thingy, beginning with the oscillator signal coming into the TIA, such that the value of cell A1 basically determined the values of the other cells on that row according to the logic associated with each column-- that is, the signal flow was A1, B1, C1, D1, E1, etc.

 

My plan was to have each row start with a different or alternating oscillator value-- that is, A1 might be 0, then A2 would be 1, then A3 would be 0 again, etc. I actually decided to randomize the value of A1 so it could be either 0 or 1 to represent the uncertainty of what state A1 would be in at the moment the TIA powered up and started receiving the oscillator's signal.

 

Most of the flow is in one direction, so it was easy to construct the logic for each cell. But as soon as I reached a point where a signal is being looped back I was faced with a quandry. How could I construct the logic for, say, cell H1 if one of its inputs is a line coming back from, say, cell P1, given that I haven't even coded the logic for cell P1 yet and determined its value?

 

What I ended up doing was add a cell in front of H1 to represent the value of P1 from further along the signal flow, but actually coming from the row above, since its state had to have been determined during a prior moment in time-- that is, G2 was equal to P1, then H2 would be determined by whatever logic represented that particular circuit, then eventually I could determine what P2 was equal to and feed its value back into G3.

 

The problem is, what to do about the very first row or moment in time? I decided to code the logic for G1 such that if we were on row 1 then we would randomly set G1 to a 0 or 1 given that we had no idea yet what its actual state should be, but if we were on any row other than row 1 then the value of G2 would be pulled from cell P1. As a result, I ended up with two rows for each state of the oscillator-- that is, rows 1 and 2 might begin with a value of 1, then rows 3 and 4 would be where the oscillator changed to a value of 0, etc. Thus, the odd-numbered rows represented the initial signal flow when the oscillator changes from 0 to 1 or vice versa, and the even-numbered rows represented the signal flow after any looped-back signals had changed their states and everything had settled down.

 

When I did that, I noticed that everywhere I was randomizing the initial state of a signal because it was being looped back from further along the path and its value wasn't known yet, that was where those asterisks appeared in the schematics. I might be wrong about what they mean, but I genuinely believe they were put there to call attention to the places where random high/low states occur at the initial moment of powering up the TIA and the oscillator.

[SeaGtGruff]

Actually, the asterisks are not where the signal comes back, but where it comes out of the whatsit-- that is, using my fictitious cell labels from above, the asterisk is not where G2 is coming back from P1, but rather is where the signal comes out of H2. But otherwise it's as I described-- the asterisks always occur at a place where the signal coming out of a circuit can have an unpredictable state upon the initial powerup, given that one or more of the signals that feed into that circuit, or which are used to latch some signal going into the circuit (if I said that right), are actually coming back from further down the overall signal path.

[+MarcoJ]

I'm silently hoping someone makes a drop-in compatible TIA alternative using an FPGA or similar.

[Smidge]

On 8/5/2023 at 5:52 PM, SeaGtGruff said:

I know this is a very late reply, but I saw this thresd and wanted to add a little to it since I spent some time several years ago trying to understand the TIA schematics and constructing an Excel spreadsheet to simulate the circuitry.

 

Those asterisks are-- I believe-- the places where you have a signal feeding backward (or looping back) into a circuit, such that the state of the whatsit will be indeterminate or random when you first start feeding power into the TIA. That might be incorrect, but the reason I believe that that's what it means is because you see those asterisks throughout the schematics and they always occur at places where a signal from further down the line is being brought back to form a loop.

 

When I was making my spreadsheet, each row represented a moment in time, and each column represented a transistor or gate or other thingy, beginning with the oscillator signal coming into the TIA, such that the value of cell A1 basically determined the values of the other cells on that row according to the logic associated with each column-- that is, the signal flow was A1, B1, C1, D1, E1, etc.

 

My plan was to have each row start with a different or alternating oscillator value-- that is, A1 might be 0, then A2 would be 1, then A3 would be 0 again, etc. I actually decided to randomize the value of A1 so it could be either 0 or 1 to represent the uncertainty of what state A1 would be in at the moment the TIA powered up and started receiving the oscillator's signal.

 

Most of the flow is in one direction, so it was easy to construct the logic for each cell. But as soon as I reached a point where a signal is being looped back I was faced with a quandry. How could I construct the logic for, say, cell H1 if one of its inputs is a line coming back from, say, cell P1, given that I haven't even coded the logic for cell P1 yet and determined its value?

 

What I ended up doing was add a cell in front of H1 to represent the value of P1 from further along the signal flow, but actually coming from the row above, since its state had to have been determined during a prior moment in time-- that is, G2 was equal to P1, then H2 would be determined by whatever logic represented that particular circuit, then eventually I could determine what P2 was equal to and feed its value back into G3.

 

The problem is, what to do about the very first row or moment in time? I decided to code the logic for G1 such that if we were on row 1 then we would randomly set G1 to a 0 or 1 given that we had no idea yet what its actual state should be, but if we were on any row other than row 1 then the value of G2 would be pulled from cell P1. As a result, I ended up with two rows for each state of the oscillator-- that is, rows 1 and 2 might begin with a value of 1, then rows 3 and 4 would be where the oscillator changed to a value of 0, etc. Thus, the odd-numbered rows represented the initial signal flow when the oscillator changes from 0 to 1 or vice versa, and the even-numbered rows represented the signal flow after any looped-back signals had changed their states and everything had settled down.

 

When I did that, I noticed that everywhere I was randomizing the initial state of a signal because it was being looped back from further along the path and its value wasn't known yet, that was where those asterisks appeared in the schematics. I might be wrong about what they mean, but I genuinely believe they were put there to call attention to the places where random high/low states occur at the initial moment of powering up the TIA and the oscillator.

That's a really interesting approach to studying the TIA and a cool find. What other observations did you make?