Side3 issues....

[candle]

side 3.0 was throughly tested, and what went into production was pretty much bullet-proof

issues arised with futher manufacturing changes enforced without such emphasis on tests, because there was no intrest in them, and there was intrest in selling cartridge

 

[magnusfalkirk]

I've got a Side 3.1, the only problem I've had with it was when I tried to upgrade the loader and managed to screw it up. Fortunately another member here offered to fix it for and was able to. Since then I've had no trouble with it. I had a U1MB installed by Crossbow, along with the UAV. Installed the Side3 plugin for the U1Mb and can run ATR's, Car images, XEX, just about anything that there is for Atari as far as images go. Only thing it doesn't run is ATX and that's no big deal since there don't seem to be many games in ATX format that aren't available in any of the other formats.

 

magnus

[Piotr D. Kaczorowski]

"Not surprising, since SRAM seems to have quite a big impact on the characteristics of the system bus" - by FJC...

 

My lab:

 

The check involved examining the reading on a selected data line of the 6502C Sally processor. In this case, the D3 line (pin 30) was chosen. Testing device: Keysight DSOX 1204G, data segment analysis mode. Atari 800XL with SELF TEST enabled. DRAM memory: 1x Sharp, 7x memory chips from Korea. In the second test, the latest revision of SRAM memory from Lotharek was used.

 

and the results...

 

 

 

DRAMs tested:

 

SRAM revision tested:

 

 

 

 

[candle]

and what exacly we're looking at? trigger was set to what?

[w1k]

maybe it will fix this issue (any many other with freezing SDX)

 

 

[Piotr D. Kaczorowski]

31 minutes ago, candle said:

and what exacly we're looking at? trigger was set to what?

Just a segment analysis to find the same pattern to compare between two sets of memory. I wanted to see if there are any noticeable differences in signal levels. It seems to me that there aren’t, but everyone can assess for themselves. If anyone wants me to perform additional tests on this set, I can do so tomorrow or the day after. I can also reinstall the DRAM.

 

As I mentioned earlier, in my opinion, the clear issues with the SRAM arise due to faulty installations. I am aware of cases where the CI and EXTSEL signals were incorrectly connected, swapped, or where EXTSEL was connected between the SRAM and other extensions without being connected to the motherboard at all (this was done by our friend Piguła).

 

I want to emphasize that the test was conducted on these specific memory modules that were presented. It may be different with others. I have not tested that.

 

By the way, I don’t want to offend anyone or start another drama, but it seems to me that the issue of SRAM and its impact on the operation of Atari is often exaggerated.

Edited September 11 by Piotr D. Kaczorowski

[_The Doctor__]

the voltage slope towards the end of the progression is flattened and low, this can be an a problem with devices and distance to external ports. I tend to agree with FJC on the point made. Depending on the crossover point and load with other items on the BUSS this can affect where in time certain devices detect or don't detect the information. Differing s-ram solutions can look worse than what you have shown us, and we would need more tests than just the limited segment shown. Candle has a valid question in that we could see and know more. Having experienced the S-RAM lottery, I'd say the solutions available need more work and standardization beyond it works for me etc. I'm glad you found something that isn't too terrible but it's still kind of a crap shoot. Show us more and pick some random modules doing a battery of duplicated tests as you go with more data over time.

Edited September 11 by _The Doctor__

[Piotr D. Kaczorowski]

15 minutes ago, _The Doctor__ said:

the voltage slope towards the end of the progression is flattened and low, this can be an a problem with devices and distance to external ports. I tend to agree with FJC on the point made. Depending on the crossover point and load with other items on the BUSS this can affect where in time certain devices detect or don't detect the information. Differing s-ram solutions can look worse than what you have shown us, and we would need more tests than just the limited segment shown. Candle has a valid question in that we could see and know more. Having experienced the S-RAM lottery, I'd say the solutions available need more work and standardization beyond it works for me etc. I'm glad you found something that isn't too terrible but it's still kind of a crap shoot. Show us more and pick some random modules doing a battery of tests as you go with more data over time.

All of you probably have more experience in this area and have seen more. It's possible that, in contrast, I might have a fresher perspective, which can sometimes be useful (quite often in IT). I connected the first available configuration to see if there would be a noticeable difference. It's possible that in the situations you're talking about, other factors appear that aren't visible here. It would be worth considering what tests to perform to check that. Either way, in new projects SRAM tends to dominate, and it's worth knowing what to expect and how to avoid certain issues.

 

Of course, an analysis using a simple SELF TEST with the ability to search for segment patterns via an oscilloscope is easy to perform, provided someone actually decides to check such things.

If necessary, we can connect a larger, faster microcontroller and scan the bus to see what's happening.

 

If you want, I can start a separate thread regarding the differences between DRAM and SRAM, so as not to clutter this one. Personally, I think that the topics of SRAM and SIDE3 are largely separate, although there may be some points of overlap.

Edited September 11 by Piotr D. Kaczorowski

[candle]

you've managed to write 6 paragraphs in 2 posts while not answering any of my questions

 

[LadyErrant]

The bus in your test is pretty unloaded, as far as modified Ataris go. I would guess that in a situation like mine (VBXE, U1MB, Rapidus, Side3) those data lines are experiencing a much greater capacitance. I was thinking about this last night and it dawned on me that replacing the 74LS08 with an F08 might be beneficial more because of drive strength than switching speed. Personally I want to plan out a series of tests to collect data at different physical locations on the PCB with progressively more addons at each iteration and see how the bus reacts. As always, time is ever the enemy. I'll get to it when I can, if $dayjob lets up some time this millennium.

[Piotr D. Kaczorowski]

13 minutes ago, candle said:

you've managed to write 6 paragraphs in 2 posts while not answering any of my questions

 

Since I measured this on the processor, on channel 1 there was synchronization on O2 (pin 39) from the processor, and that’s where the trigger was. On the second channel, the D3 line and automatic segment analysis. In place of the 74LS08 on the board, a 74F08 chip was installed.

 

What might raise some concerns is the distinction between 0 and 1. The 1 in the first element on the left starts at 2.10V, and in the DRAM version, it might be slightly higher.

[+mytek]

19 minutes ago, LadyErrant said:

t dawned on me that replacing the 74LS08 with an F08 might be beneficial more because of drive strength than switching speed.

Agreed. I'm thinking that some of the remaining problems after doing this could also benefit from some signals having increased drive as well (e.g., data bus). Overall the signal pins on the CPU are all pretty weak.

[Piotr D. Kaczorowski]

20 minutes ago, LadyErrant said:

The bus in your test is pretty unloaded, as far as modified Ataris go. I would guess that in a situation like mine (VBXE, U1MB, Rapidus, Side3) those data lines are experiencing a much greater capacitance. I was thinking about this last night and it dawned on me that replacing the 74LS08 with an F08 might be beneficial more because of drive strength than switching speed. Personally I want to plan out a series of tests to collect data at different physical locations on the PCB with progressively more addons at each iteration and see how the bus reacts. As always, time is ever the enemy. I'll get to it when I can, if $dayjob lets up some time this millennium.

 

I own two Rapidus powered Ataris and about 3 other machines at home build for others. 

 

 

 

In this machine SIDE 3.1 works in IDE+ "C":

 

 

[Piotr D. Kaczorowski]

28 minutes ago, LadyErrant said:

The bus in your test is pretty unloaded, as far as modified Ataris go. I would guess that in a situation like mine (VBXE, U1MB, Rapidus, Side3) those data lines are experiencing a much greater capacitance. I was thinking about this last night and it dawned on me that replacing the 74LS08 with an F08 might be beneficial more because of drive strength than switching speed. Personally I want to plan out a series of tests to collect data at different physical locations on the PCB with progressively more addons at each iteration and see how the bus reacts. As always, time is ever the enemy. I'll get to it when I can, if $dayjob lets up some time this millennium.

 

Ok.. I have idea for tests.. Rapidus + different CPUs from NCR, Rockwell, UMC.  Some of them will not work and will cause the problems.  So it will be possible to compare system bus with different processors.

 

[Piotr D. Kaczorowski]

On 9/10/2024 at 1:46 PM, candle said:

side 3.0 was throughly tested, and what went into production was pretty much bullet-proof

issues arised with futher manufacturing changes enforced without such emphasis on tests, because there was no intrest in them, and there was intrest in selling cartridge

 

My 3.1 works well, but it is a standard version with JAD 1.3 and firmware 0.47. The previous model, 3.0, works almost as well. I encountered two problems: one with the 'R' device and another with the Atari XEGS, which lacks Buffered PHI0. I performed a test on a different 130XE board where I replaced the 74LS08 socket with a precision socket, leaving out some legs responsible for buffering the PHI0 signal. I then connected Antic PHI0 directly to Sally's PHI0, similar to the XEGS setup. This resulted in less noise on the picture, but, like the XEGS, that 130XE did not recognize SIDE 3.0 at all.

[Piotr D. Kaczorowski]

1 hour ago, _The Doctor__ said:

.. this can be an a problem with devices and distance to external ports ..

 

I will check it on 800XL with cart inserted via cart extender when I can connect probes, but on Atari XE, SRAM is placed under processor that is very close to CART port. 

[candle]

if trigger was set on phi2, and sequence was matched on d3, then there is no way of telling if data present on D3 is read or written, or if this is RAM, ROM or perhaps hardware register, OR if CPU is driving the bus

pretty useless I must say

 

[flashjazzcat]

3 hours ago, Piotr D. Kaczorowski said:

"Not surprising, since SRAM seems to have quite a big impact on the characteristics of the system bus" - by FJC...

If I am wrong, then why the Hell was SRAM advertised as a solution to stability issues with certain devices? Pick one position or the other.

[+Stephen]

1 hour ago, flashjazzcat said:

Pick one position or the other.

Whatever lotharek decides to sell is the correct choice of course!  Shitty unshielded cables (because "I bought buckets of them, too bad if they don't work"), O2 fixer (because "74F08 is too cheap and an incorrect choice"), etc.  We see where this is going.

[Piotr D. Kaczorowski]

6 hours ago, flashjazzcat said:

If I am wrong, then why the Hell was SRAM advertised as a solution to stability issues with certain devices? Pick one position or the other.

I neither live nor work in Piekary Śląskie 🤣🤣🤣

[Piotr D. Kaczorowski]

7 hours ago, flashjazzcat said:

If I am wrong, then why the Hell was SRAM advertised as a solution to stability issues with certain devices? Pick one position or the other.

 

Typical installation of SRAM by avarage customer:

 

Long wires CI/EXTSEL... Last picutre - no comment... 

 

 

---------------------------------

 

Short connections, good quality single core wire:

 

 

 

In my opinion, DRAMs without any installation documentation will be much easier for the average user to install.

 

 

 

Edited September 12 by Piotr D. Kaczorowski

[PE1PQX]

This topic changes from Side 3 problems to memory differences...

Oh well... things just happens. 🤷‍♂️

[flashjazzcat]

On 9/7/2024 at 2:40 PM, flashjazzcat said:

'Works here' and 'you must have installed it wrong' are of course part of a refrain which has been ringing out for years which it comes to some of the devices under discussion, the presence of which is generally unhelpful when it comes to trying to isolate issues for which SIDE3 is actually responsible.

Well, I called it right a few days ago. Clearly the SRAM installation instructions should stipulate all wiring contains only 45 and 90 degree turns - then it works as intended.

Edited September 12 by flashjazzcat

[_The Doctor__]

On 9/12/2024 at 3:08 AM, PE1PQX said:

This topic changes from Side 3 problems to memory differences...

Oh well... things just happens. 🤷‍♂️

I forgot what we were talking about, that may be a memory difference.

[PE1PQX]

An update on my Side 3 cart:

4 weeks ago I sent my cart to @flashjazzcat to have a look at it.
Turned out it had a 'bad loader flash', and flashjazzcat took care of this and sent me back my cart.
(As a bonus, we had a very pleasant chat here on Atari-age)

I have tried to load a .rom file, it booted up very quickly. Same goes for a .car file.
Played around with FDISK and FORMAT in SpartaDOS  (setting up a SD-card including copying files from a PC), but I still need to figure out how this exactly works. (including partition sizes etc. in short: RTFM!).

So far I am less 'fed up' with it.

Edited September 25 by PE1PQX