Wanted: ICD RAMBO XL Schematic

[Mathy]

Hello guys

 

Could you please leave an empty line between pictures?  It would be so much easier on the eyes.

 

Sincerely

 

Mathy

 

[reifsnyderb]

This is about as far as I can get because there are connections under some of the chips.

 

[reifsnyderb]

Ok.  I looked at this even more.  This is what I think it is after studying data sheets and trying to figure out how it would work.  Looking at the connections on the bottom, there is some evidence that this may be correct.  I marked all of the lines that I had to make an educated guess at with a "G".  I think U2 is correct.  I do have reservations about my guesses on the OR gates as shown with the "G" on those lines.

 

 

 

Edit:  U3 Pin 4 didn't look right.  There is better evidence on the underside of the board that this new image may be more accurate...but it's still a "best guess".

Edit:  In the first paragraph I had U3 when I meant U2.

 

 

 

 

Edited August 3, 2022 by reifsnyderb

[ClausB]

My hat is off to the designer of this circuit. Using the spare output of the LS158 to invert A14 allows use of the simpler LS32 over my LS139, and a speed increase on MA8 of about 10 ns. Bravo!

 

I would love to see the original newsletter article.

 

Edit:

@reifsnyderb, I concur with your best guess.

Edited August 3, 2022 by ClausB

[reifsnyderb]

38 minutes ago, ClausB said:

My hat is off to the designer of this circuit. Using the spare output of the LS158 to invert A14 allows use of the simpler LS32 over my LS139, and a speed increase on MA8 of about 10 ns. Bravo!

 

I would love to see the original newsletter article.

 

Edit:

@reifsnyderb, I concur with your best guess.

I am still not happy with it and think it's wrong.  This is because if banking is enabled (PORTB bit 4= low) then MA6 and MA7 = PB2 and PB3, respectively, thereby creating a conflict with the addresses of A14 and A15.  MA8 is still high unless either PB5 or PB6 go high.  This is the truth table I've come up with.  I think that unless MA8 goes low when banking there will be corruption unless either PB5 or PB6 go low.

 

Where A14=1, A15=0

   PB
S  4  5  6    MA8

L  H  x  x    H
H  H  x  x    H
L   L  L  x    H
H   L  x  L    H
L   L  H  x    L
H   L  x  H    L

 

x = doesn't matter

 

 

 

 

 

[ClausB]

34 minutes ago, reifsnyderb said:

This is the truth table I've come up with.

I don't follow. Maybe expand it to include PB2&3.

 

The LS153 in your schematic is wired equivalently to mine (the 2 muxes are swapped), except for pin 13. I think it should go to LS158 pin 13, not 12. You can see a yellow wire through the holes from the underside but it's hidden from the top side view by the PB wires. (The neatness of the build is working against us here!)

[reifsnyderb]

6 minutes ago, ClausB said:

I don't follow. Maybe expand it to include PB2&3.

 

The LS153 in your schematic is wired equivalently to mine (the 2 muxes are swapped), except for pin 13. I think it should go to LS158 pin 13, not 12. You can see a yellow wire through the holes from the underside but it's hidden from the top side view by the PB wires. (The neatness of the build is working against us here!)

If PB2 and PB3 are replacing A14 and A15 when banking is enabled then something else has to change otherwise the "bank" will be in and over-write the main memory.  With the schematic I've come up with, MA8 is the only thing that looks like it would change and it doesn't change unless PB5 and PB6 change.  I think I'll have to make up some sort of memory map and review the schematic to see if I can find the error.  (I was going to simulate the circuitry but found that the "Digital" program doesn't have LS153's or LS158's.)

 

I agree that it's possible that LS153/13 should go to LS158/13 and this would make more logical sense.  Originally I was thinking this was the case but it is inconclusive due to the neatness of the build that you mention.  I don't think this connection matters too much as an inverted address, in this case, should be fine as long as it's consistent.  If the board were to be remade, I'd move it as you suggest just to make it a little more "logical" from a human perspective.

 

 

[ClausB]

17 minutes ago, reifsnyderb said:

With the schematic I've come up with, MA8 is the only thing that looks like it would change and it doesn't change unless PB5 and PB6 change.

MA6 and MA7 also change. I think it's OK.

 

18 minutes ago, reifsnyderb said:

I don't think this connection matters too much as an inverted address, in this case, should be fine as long as it's consistent.

It does matter to the mapping of the base 64K RAM into the extra banks.

[reifsnyderb]

26 minutes ago, ClausB said:

MA6 and MA7 also change. I think it's OK.

 

It does matter to the mapping of the base 64K RAM into the extra banks.

Ok.  I'll need to study it more as I feel I am missing something.  But maybe it's all ok.  I just want to make sure that it all will work and that I understand it.   ?

 

[ClausB]

Here's how I understand it:

 

Define:

MAx (x=0-8) are the multiplexed address signals going to the DRAMs.

RAx (x=0-17) are the demultiplexed address signals in the DRAMs.

MA8 = RA17 / RA16 (column / row)

MA7 = RA15 / RA7

MA6 = RA14 / RA6

Then the function table is:

LS32-3  RA17  RA16  RA15  RA14  RA7  RA6
   1      1     1    A15   A14   A7   A6   (Base 64K)
   0    /PB6  /PB5   PB3   PB2   A7   A6   (16 Banks)

Edit: corrected table.

Edited August 3, 2022 by ClausB

[reifsnyderb]

9 minutes ago, ClausB said:

Here's how I understand it:

 

Define:

MAx (x=0-8) are the multiplexed address signals going to the DRAMs.

RAx (x=0-17) are the demultiplexed address signals in the DRAMs.

MA8 = RA17 / RA16 (column / row)

MA7 = RA15 / RA7

MA6 = RA14 / RA6

Then the function table is:

LS32-3  RA17  RA16  RA15  RA14  RA7  RA6
   1      1     1    A15   A14   A7   A6   Normal 64K
   0     PB6   PB5   PB3   PB2   A7   A6   Banks

 

Your function table lays it out nicely!

 

My concern is that RA17 and RA16 only change if PB6 and/or PB5 are set to 1.  So, if PB5 and PB6 are both zero, the following condition exists:

 

LS3-3     RA17               RA16                RA15       RA14     RA7    RA6

1            1                    1                      A15         A14       A7      A6

0            PB6=!0=1       PB5=!0=1         PB3=0     PB2=1   A7      A6

 

This is the same memory location.

 

So I believe the schematic I created is missing something.  (The memory test screen posted shows 192k...so there shouldn't be any banks into the main memory.)

 

A thought just occurred to me:  Am I getting this confused because 4 banks are within the main memory but not shown on the memory test screenshot?

 

 

[ClausB]

Oops, got my own table wrong. Corrected previous post. PB6 & PB5 go through the LS158 which inverts them.

1 hour ago, reifsnyderb said:

Am I getting this confused because 4 banks are within the main memory but not shown on the memory test screenshot?

Yes, banks $83, $87, $8B, and $8F do mirror the base 64K RAM, so they don't show up in the XRAM Test. There was a thread a few years ago about fixing this test to show that more clearly.

 

And before someone condemns the design for mirroring base RAM, note that bank 8F is especially useful, giving full access to the 16K RAM behind the ROM and I/O registers without having to disable the OS ROM.

Edited August 3, 2022 by ClausB

[reifsnyderb]

1 hour ago, ClausB said:

Yes, banks $83, $87, $8B, and $8F do mirror the base 64K RAM, so they don't show up in the XRAM Test. There was a thread a few years ago about fixing this test to show that more clearly.

Thanks!  That explains my confusion.    ?

[TZJB]

And there was me expecting that someone would instantly know the designer of my submission ?.

Let me know if you need me to verify anything as I have had to put all my Ataris away, except for this 800XL, due a family gathering at the weekend.

The chances of me finding the original text file for this are minimal at present as there is too much stuff to go through. I started on Atari ST's and am now concentrating on XL/XE hardware at the moment and I am pleased to say that except for a couple of faulty keyboards, a couple of processors and lots of RAM in XE designed hardware, including the 800XLF, most of it seems to still be working.

Anyway I attach another 800XL Rambo XL upgrade from the 1980's this time with credit to ClausB. I didn't build this one as it's too neat for me. I did install it though. I hope that you like it.

 

 

 

 

 

[reifsnyderb]

On 8/1/2022 at 9:52 AM, TZJB said:

I can't remember what 800XL RAM upgrade this one is but it tests as 192K plus 64K main memory. It was my first 800XL and my first upgrade attempt mid 1980's from a text file I downloaded from a BBS.

I have just put the HI_OP_MA OS in and it now works great at high speed with the Sdrive-Max - once I disconnected the two SIO capacitors. I didn't have that problem with the XE's strangely.

If someone wants to try this out sometime, here's the files.  I also designed a board for it and have the gerbers in the .zip file as well.

 

TZJB 256k Upgrade.zip

 

 

 

 

Edited August 17, 2022 by reifsnyderb

[TZJB]

On 8/17/2022 at 4:19 AM, reifsnyderb said:

If someone wants to try this out sometime, here's the files.  I also designed a board for it and have the gerbers in the .zip file as well.

 

TZJB 256k Upgrade.zip 42.67 kB · 10 downloads

 

 

 

 

 

I have solved the mystery! Your board design is much neater than the original. I finally found a copy of the original 256K 800XL article! It also includes 2 100nF capacitors and several resistors. It credits ClausB and Mike Redmond but is not as I remembered from a BBS file, but from Monitor Magazine No. 19! The article is attached as a PDF if you you don't have that magazine to hand.

 

 

800XL 256K upgrade.pdf

[reifsnyderb]

31 minutes ago, TZJB said:

 

I have solved the mystery! Your board design is much neater than the original. I finally found a copy of the original 256K 800XL article! It also includes 2 100nF capacitors and several resistors. It credits ClausB and Mike Redmond but is not as I remembered from a BBS file, but from Monitor Magazine No. 19! The article is attached as a PDF if you you don't have that magazine to hand.

 

 

I just checked my schematic with the article.  My guesses were correct.  🙂

 

One mystery does remain and that is the article schematic shows Pin 3, from 74LS32, going to PB7.  I believe this is a mistake in the article's schematic.  Nowhere in the article does it mention connecting to PB7 and if your board had another external connection I hope I would have noticed it.  It appears that PB7 would be connecting to PORTB bit 7 as all of the other PBx connections refer to PORTB of the PIA.  However, connecting an output of the OR gate to PIA bit 7 would not be a good thing.  So, I think the article's schematic has an error in regards to PB7.  

 

I suspect those 100nF capacitors were supposed to be bypass capacitors.

Edited September 20, 2022 by reifsnyderb

[TZJB]

14 hours ago, reifsnyderb said:

 

I just checked my schematic with the article.  My guesses were correct.  🙂

 

One mystery does remain and that is the article schematic shows Pin 3, from 74LS32, going to PB7.  I believe this is a mistake in the article's schematic.  Nowhere in the article does it mention connecting to PB7 and if your board had another external connection I hope I would have noticed it.  It appears that PB7 would be connecting to PORTB bit 7 as all of the other PBx connections refer to PORTB of the PIA.  However, connecting an output of the OR gate to PIA bit 7 would not be a good thing.  So, I think the article's schematic has an error in regards to PB7.  

 

I suspect those 100nF capacitors were supposed to be bypass capacitors.

Yes your diagram was spot on! Exceptional deduction 👍 well done.

 

As you suggest, PB7 is not required as there are enough bank switching bits for 256K without it. I ignored that at the time as the document makes no mention of it. Compy Shop upgrades use PB6 & PB7 but the decoder logic normally allows Self Test and ANTIC banking whereas this decoder disables ANTIC banking similar to the RamboXL.

 

The 100nF capacitors are there to de-couple the board logic chips from the power. Without seeing the underside of the board it is difficult to see where they are connected but one is next to the 74LS32. I only used one 100nF capacitor on my board.

 

I am thinking that the PCB shown in the article has a space for another logic chip to enable a 512K upgrade, which is when the second 33 Ohm resistor and PB7 would be required. The 3K3 resistor seems to be a pull-up or pull-down for something and is obviously not needed as it works fine without it.

[+x=usr(1536)]

On 6/9/2022 at 6:00 PM, mytek said:

@mytek: Quick question, just to confirm: the resistor at R1 is 33Ω, not 330, 3K3, etc., correct?

 

Trying to make sure that I'm only placing one order for multiple BOMs

[+mytek]

5 hours ago, x=usr(1536) said:

@mytek: Quick question, just to confirm: the resistor at R1 is 33Ω, not 330, 3K3, etc., correct?

 

Trying to make sure that I'm only placing one order for multiple BOMs

33 ohms it is

[+x=usr(1536)]

Just now, mytek said:

33 ohms it is

Cool.  Thanks!

[+x=usr(1536)]

OK, another two questions

 

1) If U4 and U5 are populated but J3 is set for the CO21697 ANTIC, are U4 and U5 effectively ignored?  I have three PCBs to build but a mix of both ANTICs in different machines.  I'd like to be able to build them all fully-populated if possible in case I ever need to swap them around.

 

2) In the following picture, each RAM IC has a continuous bodge wire running chip-to-chip on pin 1 (A8).  Is this required for the RAMBO II-XL, or can I safely remove it?

 

 

I'm also not sure why that pin 5-to-pin 5 jumper is there, either - it's A0 to A0.

[+kheller2]

Isn’t that pin one of the RAM chips? You are looking at it from the bottom.  And that line should have already been connected component side unless this revision doesn’t have that. 

[+x=usr(1536)]

18 minutes ago, kheller2 said:

Isn’t that pin one of the RAM chips? You are looking at it from the bottom.  And that line should have already been connected component side unless this revision doesn’t have that. 

No, you're right - it is pin 1 (A8).  My mental ability to flip things on their axes isn't always the best.  Correcting that above.

 

When you mention 'already connected component side', are you referring to the motherboard having traces for the connection, or it being jumpered on the top side?

[+kheller2]

13 minutes ago, x=usr(1536) said:

No, you're right - it is pin 1 (A8).  My mental ability to flip things on their axes isn't always the best.  Correcting that above.

 

When you mention 'already connected component side', are you referring to the motherboard having traces for the connection, or it being jumpered on the top side?

There should be traces on the top side and then all routed to R32 then to +5, which is why this is lifted for standard 256K upgrades.