Another curiosity - SIDE3/U1MB/SRAM 64k

[Piotr D. Kaczorowski]

@mytek,

 

Quote

 I doubt that it will require lifting pins on Antic and GTIA and then feeding them with independent B02 from the 02 Fixer.

 

 

In my computer, the O2/Fixer is used to supply the twin BO2 to Ultimate 1MB. The remaining issues are resolved differently. Antic is located in the VBXE adapter and in general, it's difficult to supply the twin BO2 signal there. GTIA doesn't need to be connected to the O2/Fixer because: 1. I have removed Freddie (VBXE+SRAM and input to the board at 3.5Mhz), I have swapped Pokey for PokeyMax, and PIA has been replaced with the new WDC NMOS PIA. The whole system runs very stably with SIDE 3.1 even in Rapidus 20Mhz mode.

[woj]

1 hour ago, Peri Noid said:

@woj Yes, you can make Sys-Check not do anything. If I'm correct, it will then buffer cartridge slot lines. Maybe it will help.

Nope, it makes things worse. Already with DRAM, the system had problems booting just with the SIDE3 plugged in, it managed once to SpartaDosX, booting to the loader or U1MB menu was not possible. Same with the SRAM, just no successful boot of any kind even once.

 

To be thorough, I also swapped the U1MB board from my other computer, and now I at least know it is very consistent, because it kept crashing the same way. I even disabled any RAM extension in U1MB, still no go. Oh, and I did try another power supply, but none of the ones that I have are stock Atari ones.

 

All in all very interesting and curious case indeed, I am out of ideas (not that I HAVE to make it work, but it does bug me...)

[Piotr D. Kaczorowski]

 

I will try to improve the stability of Rapidus-Ultimate 1MB-SIDE3.1 on 800XL on Sunday and Monday. We'll see if there are any surprises...

 

 

[Peri Noid]

Of course, there will be plenty.

[Piotr D. Kaczorowski]

58 minutes ago, Peri Noid said:

Of course, there will be plenty.

 

If everything works, it's boring

 

 

 

 

in the meantime... motherboard has been prepared for tomorrow  

 

Edited September 30, 2023 by Piotr D. Kaczorowski

[+scorpio_ny]

On 9/28/2023 at 4:47 PM, Peri Noid said:

My guess is, the CPU adapter you're using to get U1MB signals is what causes problems. I'd suggest taking the signals from the board as adviced by Candle. Especially the O2 (Phi2) signal.

Hi @woj,

 

I have to concur with @Peri Noid that the issue probably the  sally adapter and here is why: I had the sally adapter made to use in my system. When I used it, it has caused the same crashes that you mentioned. I also have a SIde 3.0, Ultimate 1MB and a Sophia in my computer. Once I removed it and picked picked up the signals at the other locations, it stabilized the system. From what I had read is the that signals have to buffered. If I recall correctly, it is no longer recommended to pick up the signals directly the CPU anymore.

 

 

[woj]

41 minutes ago, scorpio_ny said:

Hi @woj,

 

I have to concur with @Peri Noid that the issue probably the  sally adapter and here is why: 

 

 

I did buy the argument that the adapter should not be used, I (now) do understand about the need for the signal to U1MB to be buffered. However, the whole discussion about my Sally adapter was besides the point - the picture is with the DRAM configuration and THIS DOES WORK in my machine, so even with the unbuffered O2 going to U1MB. In the SRAM configuration that gives me the headache, Sally adapter was never in use. I did use the unbuffered O2 output of the SRAM module, now I do not, the system still does not accept SIDE3.

 

Now, there is some clue in this whole story - I should not have been using unbuffered O2 for U1MB, because it makes the system unstable, and the general advise is not to do it, DRAM or not. It works totally fine on my machine with DRAM and all the add-on devices, it shouldn't according to the general public.... So perhaps there is something in there somewhere that makes both DRAM/unbuffered O2 work when it shouldn't, and SRAM/buffered O2 not work when it should... Do you see my point? Something else too slow or too fast? 

 

[+mytek]

21 minutes ago, woj said:

...the system still does not accept SIDE3.

 

Back before there was a Side3, it was acceptable to get Phi2 directly from the CPU for the U1MB. And it did work for a lot of people who also were using Side2 along with it. Also there were a lot of those installations that still had the original 74LS08 retained as the buffer.

 

However if my memory serves me correctly, issues started to be seen when a VBXE and especially a Rapidus were added to the equation. Sometimes, but not always this aberrant behavior could be corrected by swapping out a 74F08 for the 74LS08, and/or swapping out different Atari custom chips for others.

 

So does your system work with an alternative to the Side3 in play? For instance, do you have good luck with other multi-carts (AVG, Side2, Ultimate, ect.)?

 

[Peri Noid]

16 minutes ago, mytek said:

Back before there was a Side3, it was acceptable to get Phi2 directly from the CPU for the U1MB. And it did work for a lot of people who also were using Side2 along with it.

Actually, I experienced problems with U1MB+Side2 long before there was Side3  And all due to signals taken directly from a CPU (or closest vias).

[+scorpio_ny]

Hi @woj

 

Which version of the SRAM module are you using? I checked Lotharek's web site and seems to be three different variants of it. The current version 3 requires some additional wiring for VBXE.

 

Also, the SRAM module has extra functionality by replacing the functionality of several IC's on the motherboard in additional to RAM. What is the guidance in reference to the original RAM and IC's? Leave them in? Remove them?

 

[woj]

39 minutes ago, mytek said:

So does your system work with an alternative to the Side3 in play? For instance, do you have good luck with other multi-carts (AVG, Side2, Ultimate, ect.)?

I do not have any other carts besides SIDE 3 (which is 3.0, literally one of the last ones before 3.1 came, 3.0 vanished from the website at Lotharek 2 or 3 days after I bought mine).

 

11 minutes ago, scorpio_ny said:

Which version of the SRAM module are you using? I checked Lotharek's web site and seems to be three different variants of it. The current version 3 requires some additional wiring for VBXE.

 

v3, freshly bought. Yes, the wiring is in place, in fact, the system with SRAM did not work without both connections made even before I installed VBXE (but it did have the U1MB at that point). So perhaps this is another clue...

 

13 minutes ago, scorpio_ny said:

What is the guidance in reference to the original RAM and IC's? Leave them in? Remove them?

To remove the DRAMS, or data line resistors, depending on the health state of DRAMs and having or not the sockets. DRAMS are removed with SRAM in, for some tests I also removed the delay line chip, but it is not (and should not be) changing anything.

 

Away from the workbench ATM, but one thing I realized is that I did not yet test with the other CPU from 130XE AND buffered O2 going to U1MB, will do that as soon as I get home.

[_The Doctor__]

taking unbuffered cpu phi o2 before buffering weakens the input signal to the buffer chip and a number of other issues as well as skews the frame when you put the buffered signal against the un-buffered signal. Why would you do that? It's best to match up timing for peripherals from near the cart/eci/pbi and normally from the same buffered source. The CPU phi line should be left alone and allowed to service the buffering chips etc. it is a known quantity, when that gets altered, you're asking for trouble.

Edited October 1, 2023 by _The Doctor__

[+mytek]

1 hour ago, _The Doctor__ said:

taking unbuffered cpu phi o2 before buffering weakens the input signal to the buffer chip and a number of other issues as well as skews the frame when you put the buffered signal against the un-buffered signal. Why would you do that?

Opps my mistake, and a reveal of my memory recall suffering from refresh glitching 😆

 

I went back and double checked myself by watching one of Jon's older videos (Time: 21:25) and although I thought the via he picked was directly connected to Phi2 (which is what the label said), in reality when I checked it on one of my 800XL boards it was actually going to pin-11 of the 74LS08 which is the output of one of its AND gates being used for buffering that signal.

 

 

[woj]

2 hours ago, woj said:

Away from the workbench ATM, but one thing I realized is that I did not yet test with the other CPU from 130XE AND buffered O2 going to U1MB, will do that as soon as I get home.

 

So that was a good call! The guilty one identified, it is the CPU, and I think I simply experienced the infamous Mexican quality in action 😕 A proper solution to having both computers working fully and resistant to all possible configurations is yet to be devised.

 

In short, the CPU from 130XE made the 800XL work with SRAM and otherwise U1MB O2 properly connected from O2/Fixer. Didn't give it a thorough test, but seeing it actually goes into the loader and allows for loading a program convinces me this is it. Now, putting the Mexican CPU into 130XE that has the same upgrades, apart from the SRAM, makes the computer "almost" work. "Almost" - SIDE3 loader starts and goes OK for about 40 seconds, then it craps itself. Now, I will be eaten alive - the 130XE has the Sally adapter and hence the O2 fed to U1MB directly from the CPU. This has never been a problem with its original CPU (I have this config for about a year now), but clearly here it would be also worth hooking to buffered O2. Then I could probably have the 130XE working stable with the Mexican CPU and 800XL working fine on both DRAM and SRAM configs with the better CPU. I will not do it now, 130XE would need to be taken apart and I have other small projects coming up not to bother with this now. The important bit is that I know where the problem is. (It might also be a good idea at this point to source a non-Mexican Sally for a spare).

 

[+mytek]

11 minutes ago, woj said:

The guilty one identified, it is the CPU, and I think I simply experienced the infamous Mexican quality in action

Congrats

 

And it only took... a lot of patience and I'm sure some hair pulling

[woj]

47 minutes ago, mytek said:

and I'm sure some hair pulling

One needs to have some left to do that 😉

[Piotr D. Kaczorowski]

 

Well... I use NCR CPUs.  There was a rumor that they might even go up to 4Mhz. They might not, but they heat up less. It seems that they run more stable than Mexico.

[woj]

8 minutes ago, Piotr D. Kaczorowski said:

 

Well... I use NCR CPUs.  There was a rumor that they might even go up to 4Mhz. They might not, but they heat up less. It seems that they run more stable than Mexico.

It does say NCR on this CPU of mine that causes trouble... ???

[Piotr D. Kaczorowski]

3 minutes ago, woj said:

It does say NCR on this CPU of mine that causes trouble... ???

Well, actually, I'm not sure what the problem was in your case. NCR is best for Rapidus, but I know that people also run it with other Sally processors. In my opinion, the issue might be with the power supply stability or incorrect wiring.

 

In the next two days, I'm going to finish setting up an Atari 800XL with Rapidus, PokeyMax, Sophia 2, SRAM, and SIDE 3.1. I usually work with the Atari XE or 600XL, so this will be a new venture for me.

 

 

[woj]

21 hours ago, woj said:

The guilty one identified, it is the CPU, and I think I simply experienced the infamous Mexican quality in action

Just to be thorough and complete, it is actually the other way round. The 130XE had the Mexico CPU on board and this is the one that made the 800XL work with the SRAM module. The 800XL has the NCR chip from Philippines and it does not work, and also caused problems in the 130XE with the O2 connected unbuffered to U1MB. Connecting U1MB to buffered O2 was a low hanging fruit, I managed to find a suitable via (on the right hand side of the CPU) that did not require to take everything out to solder to, and managed to do it in situ. Now the NCR CPU also works with the 130XE.

 

Curious those little things, I think I just experienced the reverse of the Mexican CPU bad fame. 

PS. No, do not panic, the holes in the table are not from the Atari ICs

Edited October 2, 2023 by woj

[+scorpio_ny]

Looking at the date code for both shows that they were produced roughly at the same time. This is interesting to see. I wonder what process/threshold they used for tolerance testing? 

Edited October 2, 2023 by scorpio_ny