ANTIC /HALT timing, Phi2, and the 6502 Sally

[reifsnyderb]

Hello,

 

I just want to confirm I am interpreting this correctly as it's hard to find exact information...

 

From my two observations:

From a scope reading, it appears that /halt goes low when Phi2 goes high.

On Newell's 256k RAM upgrade, /HALT is tied to the D of a latch and RAS is tied to the clock of the latch.

 

For obvious reasons, stopping the processor in the middle of it's cycle, when Phi2 rises, isn't going to work out all that well.  Therefore, I think the timing is this:

 

1.  ANTIC issues a /HALT signal around the rise of Phi2.

2.  The 6502 Sally processor waits until Phi2 falls then halts.

3.  When finished, ANTIC raises /HALT around the rise of Phi2

4.  The 6502 Sally processor continues when Phi2 falls.

 

If this is the case, a memory expansion, that handles XE ANTIC banking, could be latched by the falling edge of Phi2 by either using Phi1 or inverting Phi2 prior to use.

 

Am I correct or missing something?

 

Thanks!

 

Brian

 

Edited November 9, 2023 by reifsnyderb

[+bob1200xl]

What is the purpose of !HALT in a memory expansion? Don't you just latch the upper addresses and run a normal memory access? PH02 going low ends the execution of the current instruction and sets up the next instruction.

 

What are you trying to do?

 

Bob

[reifsnyderb]

11 minutes ago, bob1200xl said:

What is the purpose of !HALT in a memory expansion? Don't you just latch the upper addresses and run a normal memory access? PH02 going low ends the execution of the current instruction and sets up the next instruction.

 

What are you trying to do?

 

Bob

I am trying to include ANTIC banking by setting PORTB bit 5 low.  /HALT would need to be monitored so that when ANTIC takes over, the correct memory bank is provided.

[+mytek]

@bob1200xl as Brian pointed out he is trying to mimic some aspects of the Antic banking scheme that a 130XE uses for it's own expanded memory. So if you look at the 130XE schematic dealing with RAM you can see how HALT is being used for that system.

 

 

Snipped from full 130XE Service Manual: 130XE Field Service Manual.pdf

[Rybags]

Does Sally care when /Halt occurs?

 

That signal acts on Sally in lieu of the old external circuitry that held the CPU clock so that the 6502 released the bus.

I should think if it occurs too early it doesnt' matter because the logic dictates that part of the cycle occurs as normal - from the CPU POV at least.

 

Edited November 9, 2023 by Rybags

[reifsnyderb]

2 hours ago, Rybags said:

Does Sally care when /Halt occurs?

 

That signal acts on Sally in lieu of the old external circuitry that held the CPU clock so that the 6502 released the bus.

I should think if it occurs too early it doesnt' matter because the logic dictates that part of the cycle occurs as normal - from the CPU POV at least.

 

Sally won't care.  But a memory expansion can't just act as soon as /HALT is detected.  (I have a dual trace scope reading that shows /HALT goes low around the time Phi2 goes high.)  Below is the schematic for a Newell 256k expansion that has been modified, as per the Newell instructions, for ANTIC banking.  The lower left connections have DEL and /HALT, which trigger the 74LS74 flip flop.  (DEL is connected to /RAS....I don't know why it's labelled DEL)  In this memory expansion, /HALT will only be latched and acted on when RAS rises.  RAS rises right after Phi2 goes low.  (See scope reading, at bottom, with RAS on top and Phi2 on bottom.)

 

I am just trying to confirm what I suspect before I get another board made.

 

 

Edited November 9, 2023 by reifsnyderb

[ijor]

Check the 800/400 schematics to see the exact HALT behavior on the CPU. The 800 (or 400) use discrete HALT logic, as you probably already know. No need to guess, or suspect, what Sally does.

 

If you want to know exactly how HALT is produced you can also check my ANTIC internal schematics.

Edited November 9, 2023 by ijor

[reifsnyderb]

3 minutes ago, ijor said:

Check the 800/400 schematics to see the exact HALT behavior on the CPU. The 800 (or 400) use discrete HALT logic, as you probably already know. No need to guess, or suspect, what Sally does.

 

If you want to know exactly how HALT is produced you can also check my ANTIC internal schematics.

Please see my first post.  I am not concerned about Sally.  I just want to confirm that an ANTIC banking and/or Compy Shop memory expansion waits until the next clock cycle prior to responding to a /halt signal.  As I get more information, I think the answer is that a memory expansion has to wait until the current cycle is over.  I believe and am trying to confirm this would lead to the following order of events:

 

1.  ANTIC pulls /HALT low.

2.  CPU finishes the current clock cycle.  (The discrete HALT logic of the 800 latches /HALT on the rising edge of Phi1.)

3.  On the Newell memory expansion, /HALT is then latched on the rising edge of RAS, prior to the rising edge of Phi2...when memory access would occur.

 

 

[ijor]

1 hour ago, reifsnyderb said:

Please see my first post.  I am not concerned about Sally.  I just want to confirm that an ANTIC banking and/or Compy Shop memory expansion waits until the next clock cycle prior to responding to a /halt signal.  As I get more information, I think the answer is that a memory expansion has to wait until the current cycle is over.  I believe and am trying to confirm this would lead to the following order of events:

 

I read your first post, of course. And I beg to differ, but I think you do are concerned about Sally, just not directly. Ultimately, the memory behavior depends on the CPU behavior on a halted cycle. If you understand when the CPU is halted, when the address bus is available and when it is tristated, and when the data bus is latched, then you know exactly how your memory should behave.

 

Yes, of course, ANTIC asserts HALT at the previous cycle. The HALT logic, either at the board level on the 400/800, or integrated in Sally, needs one cycle (actually half, depends on the point or view) to process it. Note that ANTIC, however, changes HALT rather late from the clock edge because it is the output of combinatorial logic, it is not registered.

 

Edited November 9, 2023 by ijor

[reifsnyderb]

5 minutes ago, ijor said:

 

I read your first post, of course. And I beg to differ, but you do are concerned about Sally, just not directly. Ultimately, the memory behavior depends on the CPU behavior on a halted cycle. If you understand when the CPU is halted, when the address bus is available and when it is tristated, and when the data bus is latched, then you know exactly how your memory should behave.

 

Yes, of course, ANTIC asserts HALT at the previous cycle. The HALT logic, either at the board level on the 400/800, or integrated in Sally, needs one cycle (actually half, depends on the point or view) to process it. Note that ANTIC, however, changes HALT rather late from the clock edge because it is the output of combinatorial logic, it is not registered.

 

Thanks!  I wasn't thinking about Sally like that and was too focused on the memory.

[_The Doctor__]

Half clock is correct and the delay in the described modified memory upgrade would more than likely make sure the memory access is stable and at the right time for that particular upgrade. There might already be a delay in the time it takes external 1090 connection and buffer to the card in the slot. Fun times with your scope ensue

 

Edited November 9, 2023 by _The Doctor__

[reifsnyderb]

45 minutes ago, _The Doctor__ said:

Half clock is correct and the delay in the described modified memory upgrade would more than likely make sure the memory access is stable and at the right time for that particular upgrade. There might already be a delay in the time it takes external 1090 connection and buffer to the card in the slot. Fun times with your scope ensue

 

Well, this helps both with getting a Compy-Shop 1090 card to work and with that new 800XL board I am working on.  I can easily add a delay by connecting a grounded capacitor (c75, below) to the latch clock pulse line. 

 

Here's what I added to the 800XL board I am working on:

 

 

I'll need to use one of the pins (i.e. 13) for a /halt latch and still have 2 other macro cells available in the event I need extra logic.

 

In the schematic above, PB2-PB5 are from the PIA chip.  SRA14-SRA16 go to pins A14-A16 on the SRAM chip.

 

For normal operation, if PB4 and PB5 are high, SRA16 will be set low, SRA14 will be equal to AR14, and SRA15 will be equal to A15.

 

With CPU banking, PB4 will be set low, /halt will have to be high, SRA16 will be set high, SRA14 will be equal to PB2, and SRA15 will be equal to PB3.

 

With ANTIC banking, the /halt latch will be checked to see if /halt is called.  If PB5 is set low and /halt is called, SRA16 will be set high, SR15 will be equal to PB2, and SRA15 will be equal to PB3.

 

The /halt latch, on Pin 13, can be configured such that .d is from pin 9 and it is triggered by sending a pulse out pin 16 when Phi2 drops.  The capacitor, C75, will ensure a slight delay on the clock pulse.  The value of this capacitor will have to be determined through experimentation.  However, it shouldn't take much.  I've used a 4.7nF capacitor for a Read/Write Late delay on an 800 board.  Something similar should work fine.  I'll have to fine tune it with the scope.

 

 

 

 

Edited November 9, 2023 by reifsnyderb

[phaeron]

The best official reference I could find is from the ANTIC datasheet, which specifies setup/hold times for /HALT relative to the falling edge of Φ2. This is shown more clearly in the CGIA datasheet:

Interestingly, this is different from the 800 schematic, which shows a flip flop latching it on the rising edge of Φ1.

 

[reifsnyderb]

6 minutes ago, phaeron said:

The best official reference I could find is from the ANTIC datasheet, which specifies setup/hold times for /HALT relative to the falling edge of Φ2. This is shown more clearly in the CGIA datasheet:

Interestingly, this is different from the 800 schematic, which shows a flip flop latching it on the rising edge of Φ1.

 

Nice!  Thank you!  ANTIC has a datasheet?  Where can I download a copy at?  (I wouldn't mind datasheets for the other chips, too.)

[phaeron]

28 minutes ago, reifsnyderb said:

Nice!  Thank you!  ANTIC has a datasheet?  Where can I download a copy at?  (I wouldn't mind datasheets for the other chips, too.)

They were made available by the Atari Historical Society -- mirrored at Pigwa:

http://ftp.pigwa.net/stuff/collections/nir_dary_cds/Tech Info/

[ijor]

43 minutes ago, phaeron said:

The best official reference I could find is from the ANTIC datasheet, which specifies setup/hold times for /HALT relative to the falling edge of Φ2.

Unfortunately the timing values on the ANTIC datasheet are completely unrealistic. In this specific case it is almost ridiculous that HALT and NMI have the same timing specifications. NMI is a registered signal but, as said, HALT it is not. That means that their timing would be completely different.

 

Quote

... relative to the falling edge of Φ2.

Interestingly, this is different from the 800 schematic, which shows a flip flop latching it on the rising edge of Φ1.

ANTIC has no (direct) access to PHI1, it makes sense to specify the timing in relation to PHI2 because that's the input that ultimately clocks that logic. At board level the falling edge of PHI2 is supposed to coincide with the raising edge of PHI1.

 

I don't think this matter too much. HALT should be latched synchronously and if you are using, as it seems, relatively modern logic, you normally don't care at all about the setup or hold time of your inputs.

Edited November 10, 2023 by ijor

[reifsnyderb]

I got a scope reading of Phi2 and /HALT.  Phi2 is on the top and /HALT is on the bottom.