Antic banking 130XE 320k upgrades and small glitches in some demos

[Beeblebrox]

Hi

I've undertaken 320k upgrades in both 65XE and 130XE systems. The process is slighly different, (65XE utilises a gal chip among other things).

 

The 130XE upgrade has an additional step to re-establish Antic banking by bridging the solder pads for the PIA pins 15 and 16 (both of the PIA pins for these are lifted but the actual pcb solder pads for them are bridged.)

 

It seems that, unlike other ram upgrades in say a stock 800XL (so rambo XL 256k for example), when you run the NEAR demo or Unmec demo on the 320K XE's, they look fine but at some stage there is a graphical glitch. The demos don't crash or anything. I've only ever seen it with those two demos and on 130XE 320k upgraded systems.

 

This is the upgrade method.

 

130XE https://exxosforum.co.uk/forum/viewtopic.php?t=732

 

I don't have the 65XE's anymore to test to see if the same issue is present.

 

Has anyone else experienced this with these 130XE 320k upgrades and is this to do with Antic banking?

 

 

 

 

 

Edited December 20, 2023 by Beeblebrox

[Rybags]

I don't quite get why you'd bridge those pads - PB5 and PB6.

Normally on 130XE, bit 5 controls if Antic sees main or extended Ram.

On some schemes >128K, it forms part of the extended bank selection.  There doesn't seem any logical reason to force bits 5-6 to the same value.

[+kheller2]

PB5 and 6 are run to a new LS158, PIN 16 of the socket, however, I'm not sure where that goes..GND?  Tying socket pin 16 to 15 and you are tying VBE to GND possibly?

[Beeblebrox]

Thanks all. I'll dedicate some time over the hols to look into it. So many projects on the go for the hols, (got a lumacode setup to complete, several upgrades including a VBXE 800 install, etc). 

[phaeron]

Tracing through the wiring directions, what this mod does is disconnect PIA PB5 and PB6 from the motherboard and multiplex them to A8 on the new RAMs based on phi2 -- making PB5 and PB6 the two additional banking bits for a 2356 banking setup. So far, so good.

 

Now, with nothing connected to PB5 on the motherboard, this is going to break ANTIC banking -- as in not just no separate ANTIC banking, but ANTIC will never see the extended bank. This is because the PB5 connection on the motherboard to the EMMU has been disconnected from the PIA and is now just being pulled up. But connecting PB5 to PB6 on the motherboard shouldn't do anything since PB6 floats on the 130XE. In general, Atari put pull-ups on the port B lines used on each computer. It's one of the goofier ways to detect the various XL/XE models.

 

I wonder if what was intended was to connect PB5 to PB4 on the motherboard instead, so that ANTIC banking would activate along with CPU banking. It still wouldn't allow for separate ANTIC access, but it would bank ANTIC and the CPU together as in a normal RAMBO setup.