+InsaneMultitasker Posted January 24 Share Posted January 24 37 minutes ago, Jeff White said: AFAIK, the level 1 source code has never been made available If by level 1 source code you mean the DSR routines for low-level SCSI access, then yes, that commented source is available to us. Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5395977 Share on other sites More sharing options...
+mizapf Posted January 25 Share Posted January 25 I remember that I translated the German SNUG comments to English in that source file; I suppose this is what you think of. Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5396014 Share on other sites More sharing options...
+InsaneMultitasker Posted January 25 Share Posted January 25 10 minutes ago, mizapf said: I remember that I translated the German SNUG comments to English in that source file; I suppose this is what you think of. Yes, for the /4a, and I used that file to validate and reconcile the Geneve source. The Geneve OS source contains the code for both ‘modes’. 2 Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5396023 Share on other sites More sharing options...
humeur Posted January 25 Share Posted January 25 My Scsi Rev E 3 Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5396450 Share on other sites More sharing options...
RickyDean Posted January 25 Author Share Posted January 25 Okay, looks like mine, except you have additional wiring and mods on the backside and the daughter board that looks like it houses a CLPD PLCC instead of the originial PALCE gals on U12 and U13 Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5396460 Share on other sites More sharing options...
+Ksarul Posted January 26 Share Posted January 26 5 hours ago, RickyDean said: Okay, looks like mine, except you have additional wiring and mods on the backside and the daughter board that looks like it houses a CLPD PLCC instead of the originial PALCE gals on U12 and U13 That's the SNUG daughter board. It is also the reason for the extra wires on the main circuit card. Note that the DSR chip is probably different as well, as I strongly suspect the "B" in V1.6B stands for Becker. 2 Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5396738 Share on other sites More sharing options...
Jeff White Posted January 26 Share Posted January 26 On 1/24/2024 at 7:19 PM, InsaneMultitasker said: Yes, for the /4a, and I used that file to validate and reconcile the Geneve source. The Geneve OS source contains the code for both ‘modes’. I meant Will McGovern's original code. Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5397141 Share on other sites More sharing options...
+InsaneMultitasker Posted January 26 Share Posted January 26 3 hours ago, Jeff White said: I meant Will McGovern's original code. What I can tell you is that we have the entire low-level code for bank 7, updated to work with the PDMA modification v1.6 and (I believe was) built on Will's original code. I do not believe that I have the v1.5 low-level code for the unmodified cards, though I wonder if it exists on an old hard drive platter. Seems to me I looked for it once before. The files would be from 1994 when Bud gathered you, Dan, me, Mike together in Indiana. We have code for higher level functions banks 0-6 but I don't know that anyone has ever reconciled them to the binary EPROM. The last high-level review I completed was in the early 2000s when we were trying to track down a bug that presumably manifested after caching a certain number of directory entries (for quick access) but it wasn't easily reproduced nor found. 3 Quote Link to comment https://forums.atariage.com/topic/359833-scsi-pals/page/2/#findComment-5397340 Share on other sites More sharing options...
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