Nano PEB Source Files Released

[Shift838]

All,

 

@InsaneMultitasker and I contacted Custodio Malilong who developed the Nano PEB and CF7 devices for the TI-99/4A to check what his current state was on development for the product.  Custodio has given his permissions to release the source files to the Nano PEB as he is no longer working on it or making updates.  So it is with great pleasure that Insane and I release the files we obtained from him to help anyone wanting to develop or improve or just see the method behind his madness.

 

Enjoy!

 

 

 

nanoPEB.s nanoSIO.s T16C550C.zip

nanoPEB_Board.zip nanoPEB_SIO.vhdl

Edited July 18 by Shift838

[Gary from OPA]

This is great news. What about the programming for the controller chip?

 

Now, I just wish the feds had returned my whole nanoPEB instead of just the compact flash and adapter part.

 

As I always had in the back of my mind to make this device better with similar features of the Horizon Ramdisk.

 

At least I can study the code, just no way to physically test it on real hardware.

 

Edited April 20 by Gary from OPA

[ti99iuc]

Wow! I really hope it can be used and updated for something new  thanks for sharing this

[+InsaneMultitasker]

I've attached the source to the modified DM1000 v3.5 that was used with the CF7 (and should be compatible with the nano)  

 

cfmgr.s.txt

[Stuart]

2 hours ago, Shift838 said:

All,

 

@InsaneMultitasker and I contacted Custodio Malilong who developed the Nano PEB and CF7 devices for the TI-99/4A to check what his current state was on development for the product.  Custodio has given his permissions to release the source files to the Nano PEB as he is no longer working on it or making updates.  So it is with great pleasure that Insane and I release the files we obtained from him to help anyone wanting to develop or improve or just see the method behind his madness.

Smashing stuff! Did you explore the possibility of getting the schematics for the various versions, or the code for the Xilinx CPLD?

 

[+OLD CS1]

Please be sure to express our thanks to Custodio!

[Shift838]

6 hours ago, Stuart said:

Smashing stuff! Did you explore the possibility of getting the schematics for the various versions, or the code for the Xilinx CPLD?

 

no, but I can ask.  Never hurts to ask.

[+Schmitzi]

 

Great news  🖐️

 

 

 

 

[Stuart]

7 hours ago, Shift838 said:

no, but I can ask.  Never hurts to ask.

Would be great if you could, if you're happy to do so. Perhaps with an emphasis on being able to diagnose/repair the broken units out there, as opposed to plans to build new ones.

 

We know there are at least three PCB layouts, one with the EEPROM and RAM as thru-hole (DIP) components, and two layouts with the EEPROM and RAM as surface mount. Would be useful to know if he swapped pins around on the CPLD between the designs, or if they all use the same CPLD pinout.

 

 

 

 

[RickyDean]

Yep the same would got for the CF7+. I have two both the have the 32k and He sent me a CPLD that would work with the 32k not installed, but installed it wouldn't work. The other I don't know if it still works or not, think the CF card was messed up, by one of my grandchildren.

[+InsaneMultitasker]

Perhaps the RS232 CRU selection "issue" can be resolved if the hardware code & schematics are released. That would allow more unpatched 9902-serial programs to run unpatched.

 

I found a few files I had forgotten about when @Shift838 and I reached out to Custodio. 

 

- Updates to MidiMaster for the Nano - version 2.3 and 2.5Z.  

- Funnelweb 4.40 patched UTIL, FW, and LOAD programs to account for the extra 8 bytes of VDP RAM the CF7/nano use.  As far as I can tell, this is the last image I released in 2011, after discovering the XB loader needed to be revised.   I included a text file that contains text from the list server post and some information about DSKU.

- Telco patch for the terminal emulator portion.  Someone had reached out to Charles Earl for the source but as far as I know, we are still waiting.

 

If I come across any related files or source, I'll post them in this topic.

MIDIMaster99-v25Z-standard-NANO AND UBERGROM.dsk MIDIMASTER V23 NANO.dsk Funnelweb40pat-nanopeb problem.dsk TELCN for nano.zip !CF7 Compact Flash FWEB DSKU fix and ideas.txt

[Kchula-Rrit]

On 4/20/2024 at 9:20 AM, Shift838 said:

All,

 

@InsaneMultitasker and I contacted Custodio Malilong who developed the Nano PEB and CF7 devices for the TI-99/4A to check what his current state was on development for the product.  Custodio has given his permissions to release the source files to the Nano PEB as he is no longer working on it or making updates.  So it is with great pleasure that Insane and I release the files we obtained from him to help anyone wanting to develop or improve or just see the method behind his madness.

 

Enjoy!

Just found this tonight!  I've been commenting-up a file I made with DiskAssembler off-and-on for a while, just to see how the thing works.  I've had to rely on the similarity to Thierry Nouspikel's commented TI code to figure out some things.  Be fascinating to compare.

K-R.

[Shift838]

I have received a couple of additional files from Custodio.  The nanoPEB_SIO vhdl file and the board files for the nanoPEB board.  I have edited and attached them in the original post.

[Jeff White]

It appears this version used a 16550 instead of 9902.  Just curious about how well that worked.

 

IIRC, the CF7 is disks and parallel port.  The nanoPEB is disks and serial port.

 

 

[Stuart]

2 hours ago, Shift838 said:

I have received a couple of additional files from Custodio.  The nanoPEB_SIO vhdl file and the board files for the nanoPEB board.  I have edited and attached them in the original post.

Good work, Shift838 

 

Looks like the schematic(s) is done in Autodesk EAGLE. Anyone have that installed already and could convert to Gerbers for easy viewing?

[Stuart]

I've attached PDFs of the PCB layout, schematic and parts list from the Autodesk EAGLE files from Custodio. Note that there are several variants of the NanoPEB so these files might not be an exact match for your particular device.

 

Is the VHDL file that Custodio provided all that is need to program a new XILINX CPLD? Also need a create a UCF(?) file to associate signals to physical pins? Any recommendations on programmers that will work with an XC9572-PLCC44?

 

nanoPEB PCB.pdfnanoPEB Schematic.pdf

nanoPEB Parts List.txt

[Stuart]

Now we have some useful files from Custodio, I done some further work on the NanoPEB that someone had sent me to try to repair.

 

An adventure into the NanoPEB design, CPLDs and VHDL. TLDR; NanoPEB now working again!

 

====

 

These notes relates to a NanoPEB with the following main ICs:

 

-- Xilinx XC9572-PC44 CPLD in a socketed PLCC package

 

-- AM29F010-90JC 128K x 8 bit EEPROM in a socketed PLCC package

 

-- UM62256EM-70LLT 32K x 8 bit RAM in a soldered SOP package.

 

The NanoPEB PCB includes a ‘bodge’ wire which connects GND from the console sideport connector to the 74HCT00 logic IC.

 

The NanoPEB schematic from Custodio (https://forums.atariage.com/applications/core/interface/file/attachment.php?id=1137840&key=814bc9d265d39f24c156fbc45a0d23e4) appears to be correct for this board with the following exceptions:

 

-- The pin numbers for the CPLD (“LOGICG”) are correct but the internal signal names are not (FBxMCy = Functional Block x Macro Cell Y). These signal names appear to be for an earlier CPLD. It doesn’t actually make any difference but don’t expect these names to match what you’ll see in the Xilinx ISE Design Suite software used later to create the programming JED file for the CPLD.

 

-- The pin numbers for the EEPROM are for a W27C512 DIL package, not the PLCC package used here. The internal signal names are correct so find the PLCC package pin number for each of those and you should be able to trace the signals.

 

The CPLD has three latched outputs BANK0, BANK1 and BANK2 which drive the EEPROM most significant address pins. These operate as follows:

 

-- BANK2 (which drives EEPROM A13) is defined as logic 0 in the CPLD VHDL, and is not used further.

 

-- When the CRU bit at >1100 is set to 1 to enable the IDE interface, BANK0 (which drives EEPROM A15) is set to 1 to select the EEPROM memory block starting at >8000. If you look at the EEPROM address >8000, you can see the start of the IDE DSR.

 

-- When the CRU bit at >1300 is set to 1 to enable the RS-232 interface, BANK1 (which drives EEPROM A14) is set to 1 to select the EEPROM memory block starting at >4000. If you look at the EEPROM address >4000, you can see the start of the RS-232 DSR.

 

The NanoPEB_SIO VHDL file from Custodio (https://forums.atariage.com/applications/core/interface/file/attachment.php?id=1135989&key=9582dd3a3dff711e1ad06eb24bfa1721) is correct for this board. This is a text file (so easy to read and edit) and contains a number of logic conditions for the CPLD inputs and defines the state of the CPLD outputs based on those conditions. Custodio has annotated some of the conditions with “1100” and “1300” etc. to identify those applicable to the IDE interface at CRU address >1100 and the RS-232 address at >1300, and if you look at the address bits in “A” and “A_LOW” in the conditions you can see how these match the addresses in the comments. Remembering that address bit A15 and CRUOUT are combined into a single signal coming out of the console helps to understand where the CRUOUT bit is latched or used.

 

The VHDL defines read access to the CF card starting at address >5F80, and write access starting at address >5FC0. These addresses are only active if the IDE interface has been enabled through CRU bit >1100.

 

To program a new CPLD, or to reprogram an existing one, requires the following software and tools:

 

-- The Xilinx ISE Design Suite software, which is used to convert the VHDL file to a JED file to program into the CPLD.

 

-- The Xilinx iMPACT tool (part of the Design Suite above) which downloads the JED file into the CPLD over its JTAG interface.

 

-- A Xilinx Platform Cable USB II interface, which provides the physical/electrical interface between the PC and CPLD.

 

-- A PLCC to 40-pin DIP converter module.

 

-- A 5V power supply to power the CPLD during programming.

 

Each of these is described below.

 

The Xilinx ISE Design Suite software is available as a free “WebPACK” edition. But you do need to set up a Xilinx account (which is easy) and (in the UK at least) I needed to provide contact details for some sort of export control check. The most recent versions of ISE don’t support the discontinued XC9500 family of CPLDs, but with a bit of research I found that ISE 12.1 does (confirmed by looking in the irn.pdf file in the software download). This can be downloaded from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html. This won’t run under Windows 10 – the latest version of Windows it supports is Windows XP, so I installed it in a copy of Windows XP running in an Oracle VM VirtualBox. You need to get a (free) certificate-based license for ISE – this is a license file that is e-mailed to you, and is provided with instructions on what to do with it.

 

Once ISE is installed, you need to create a new project using the wizard and selecting source type “VHDL Module”, and referencing the nanoPEB_SIO.vhdl file. You need to add to the project the attached nanoPEB_SIO.ucf ‘user constraints’ file which associates the input and output signals with physical pins (there is a built-in graphical tool for associating signals and pins to build the ucf file but I can’t remember how to access it).

 

To process the files into a JED file, click Process > Implement Top Module. This create a .jed file within the project as well as a multitude of reports, some of which contain errors. These seem to relate to advice not to create 1-bit latches, and “global clock designation (BUFG) on signal xxx” errors on the signals input through the CPLD global clock inputs (GCK0/1/2). Everything seemed to work if these were just ignored.

 

To program the JED file into the CPLD, click Tools > iMPACT to run the iMPACT utility. You need to use the “Boundary Scan” flow. You need a Xilinx Platform Cable USB II interface cable. I was able to get a used, genuine Xilinx one from eBay. If getting a Chinese knockoff, read the description carefully as some of these claim not to support the XC9500 family devices. (The Xilinx originals seem to have a serial number on the label, the Chinese ones do not.) Getting the Windows XP VirtualBox to recognise the USB cable can be a bit of a pain.

 

The CPLD needs to be powered during programming, and you need to be able to connect the interface cable to the CPLD JTAG pins. So I got a PLCC to 40-pin DIP converter module. The pins on this are NOT wired 1-to-1, and 4 PLCC pins are not connected (as the PLCC has 44 pins). So work out from the CPLD datasheet where the power pins are (3 pins for Vcc, 3 pins for GND), then work out which of the DIP pins these are connected to, then wire them together, with flying leads to connect to a 5V power supply. One of the PLCC CPLD GND pins was not connected to a DIP pin, so I had to identify and solder a wire to one of the pads on the module PCB. I also connected a 0.1uF decoupling capacitor across two of the supply pins. Work out which of the DIP pins are for the JTAG interface and connect these to flying leads on the interface cable, along with GND and Vcc (“VRef”).

 

Once everything was connected and powered, iMPACT recognised the XC9572 CPLD and erased, programmed and verified it within a couple of minutes.

 

=====

 

With regards the faulty NanoPEB that I was trying to repair, once I had checked the NanoPEB for any obvious bad solder joints and some general ‘faffing about’, I investigated it using MiniMem EasyBug and a logic probe. It is well known that if you enable a peripheral by setting its CRU base address bit to 1, you should be able to read its DSR starting at memory address >4000. This worked fine for the RS-232 interface at >1300, but trying the same technique for the IDE interface at >1100 resulting in all >00’s being read for the DSR. Checking the outputs of the CPLD, enabling each interface set the relevant BANKx address input to the EEPROM as described earlier, and disabling each interface reset the relevant BANKx line. Checking the EEPROM /CE input, there was a pulse on this each time a byte of the DSR was read for the RS-232 interface, but no pulses when reading the DSR for the IDE interface, hence the >00 bytes. So it looked like there was an internal problem with the BANK0 latch. First I tried simply reprogramming it but this didn’t solve the problem. The next ‘easy’ thing to do would be to program and try a new CPLD, but the one I bought off eBay was sent as a surface mount package so was no good and I was getting frustrated to wait for a replacement.

 

So a plan to try … there are three latched BANKx outputs from the CPLD as described earlier, and these drive address pins on the EEPROM. Only BANK0 and BANK1 are used, and the BANK0 latch appears to have an internal fault. BANK0 selects the EEPROM memory block starting at >8000. So I modified the VHDL and swapped references to BANK0 to BANK2 and vice versa, then reprogrammed the CPLD (with much cursing trying to get the USB interface cable recognised in the VirtualBox VM). BANK2 selects the EEPROM memory block starting at >2000, so I modified a dump of the EEPROM by copying memory block >8000 - >9FFF to >2000 - >3FFF, then reprogrammed the EEPROM. Switch on and it worked!

 

One strange observation – even before repair, the console title screen included the “NanoPEB – V1” which comes from the IDE DSR. So not sure how the console accessed this when executing the peripheral DSR power-up routines if the IDE DSR could not be accessed afterward.  ???

 

nanoPEB_SIO.ucf

NanoPEB EEPROM Dump.bin

Edited August 10 by Stuart