If you could purchase PCB's that fit shells other than Atari's.......

[CPUWIZ]

.. which company EPROM PCB would you like to see made?

[Shawn]

Parker for sure. Coleco shells are easy to get "Atari" boards into them but Parker Bros shells are a pain to fit with an Atari PCB. It would be nice not to have to cut at shell with razor blade to fit a new PCB and not have to use hot glues to make the boards stay put and not rattle around on the inside of the carts.

[CPUWIZ]

Seems like not too many people actually care about this sort of thing. Interesting, thanks for voting so far, any company I should add?

[PacManPlus]

Activision?

[Zach]

Voted for Parker Brothers. Of course a bonus would be if it could handle PB's bankswitching.

[Bruce Tomlin]

Voted for Parker Brothers. Of course a bonus would be if it could handle PB's bankswitching.

Well, since it is a whole new board we're talking about here, that would be a great idea, with just a couple of jumpers to bypass the holes for non-bankswitched.

[vdub_bobby]

The Parker Bros. bankswitch scheme is just the E0, right? That weird 8K bankswitch scheme? Are the advantages of this, over standard F8 8k bankswitching, big enough to justify supporting this? It seems like the main point to supporting E0 bankswitching would be so that pirate/repro copies of PB games could be made.

[Bruce Tomlin]

The Parker Bros. bankswitch scheme is just the E0, right? That weird 8K bankswitch scheme? Are the advantages of this, over standard F8 8k bankswitching, big enough to justify supporting this? It seems like the main point to supporting E0 bankswitching would be so that pirate/repro copies of PB games could be made.

There are only two or three games that have not been converted out of ten or so, one of which has been converted but is unreliable.

 

This would also allow homebrews using E0, but is that really worth the effort since we have 3E? Hacks maybe, but not homebrews. Especially since E0 requires at least two chips, one of which is a RAM chip, and a board design for just for E0 isn't really worth it.

[Kroko]

This would also allow homebrews using E0, but is that really worth the effort since we have 3E?

AFAIK, there are no boards available to homebrewers that support additional RAM. Yes, there are a few prototypes, like 3E or 4A50, but homebrewers can't buy or actually use them at this time.

 

Especially since E0 requires at least two chips, one of which is a RAM chip

Don't mix it with E7. E0 does not need any RAM

[vdub_bobby]

Especially since E0 requires at least two chips, one of which is a RAM chip

Don't mix it with E7. E0 does not need any RAM

That's what I thought. E0 is just an oddball 8K bankswitch scheme that I'm sure does have some advantages over F8 - but I just don't see that it has that many advantages to justify the effort to create a board that supports it. I'd rather see a board that supports the superchip RAM or something else similar first.

[Bruce Tomlin]

This would also allow homebrews using E0, but is that really worth the effort since we have 3E?

AFAIK, there are no boards available to homebrewers that support additional RAM. Yes, there are a few prototypes, like 3E or 4A50, but homebrewers can't buy or actually use them at this time.

 

Especially since E0 requires at least two chips, one of which is a RAM chip

Don't mix it with E7. E0 does not need any RAM

http://www94.pair.com/jsoper/2600_pb_bs.html

 

Then tell me what that 74170 is. E0 requires 9 bits of RAM, three bits each in three rows.

[Shawn]

Especially since E0 requires at least two chips, one of which is a RAM chip

Don't mix it with E7. E0 does not need any RAM

That's what I thought. E0 is just an oddball 8K bankswitch scheme that I'm sure does have some advantages over F8 - but I just don't see that it has that many advantages to justify the effort to create a board that supports it. I'd rather see a board that supports the superchip RAM or something else similar first.

 

 

SARA is comming out to party VERY soon, Trust me.

[CPUWIZ]

This would also allow homebrews using E0, but is that really worth the effort since we have 3E?

AFAIK, there are no boards available to homebrewers that support additional RAM. Yes, there are a few prototypes, like 3E or 4A50, but homebrewers can't buy or actually use them at this time.

 

Especially since E0 requires at least two chips, one of which is a RAM chip

Don't mix it with E7. E0 does not need any RAM

http://www94.pair.com/jsoper/2600_pb_bs.html

 

Then tell me what that 74170 is. E0 requires 9 bits of RAM, three bits each in three rows.

 

It sure as hell isn't called RAM.

 

http://www.xs4all.nl/~ganswijk/chipdir/giicm/74170.txt

[Kroko]

Then tell me what that 74170 is

 

Its a 4x4 register file with open collector output I am sure you already knew this.

But seriously. You should not call a chip RAM just because it has a few registers inside.

In that case you would also have to call the standard F8, F6, F4 bankswitching boards

"RAM" boards. You can fit E0 in a standard PLD without needing a RAM chip, that is what

I wanted to say

[CPUWIZ]

Well, looks like Parker it is then. It will be fully compatible with normal F4,F6 and F8 bankswitching PLD's. First prototype should arrive from China next week.

[Happy_Dude]

Is it too lat to vote for Imagic

Edited June 10, 2006 by Happy_Dude

[supercat]

Its a 4x4 register file with open collector output I am sure you already knew this.

But seriously. You should not call a chip RAM just because it has a few registers inside.

In that case you would also have to call the standard F8, F6, F4 bankswitching boards

"RAM" boards. You can fit E0 in a standard PLD without needing a RAM chip, that is what

I wanted to say

 

What is a RAM, if not a collection of registers which is addressable for both reading and writing?

 

The 74170 is called a "register file" because it's more likely to be used for holding registers within a CPU core than as memory outside one. Functionally, though, if one opened up a 2600, used a 74138 to decode read and write addresses in the range $00-$7F, and threw in a 74170 (tying both sets of data pins to D0-D3, and both sets of address pins to A0-A1), the effect would be to add four nybbles of RAM to the 2600. Too small a quantity to be useful for much, but RAM nonetheless.

 

BTW, how do you fit PB bankswitching into a "standard" PLD? A CPLD like the XC9536XL would have no problem, but the smallest PLD I would expect to be usable would be a 26V12, and those have been largely superceded by CPLD's.

 

At minimum you need 13 address inputs, a timing input, a chip-select output, a timing output, and nine banking outputs (use tri-stating to select among them, and pullups to establish a default). So 14 inputs and 11 outputs.

Edited June 10, 2006 by supercat

[+batari]

Its a 4x4 register file with open collector output I am sure you already knew this.

But seriously. You should not call a chip RAM just because it has a few registers inside.

In that case you would also have to call the standard F8, F6, F4 bankswitching boards

"RAM" boards. You can fit E0 in a standard PLD without needing a RAM chip, that is what

I wanted to say

 

What is a RAM, if not a collection of registers which is addressable for both reading and writing?

 

The 74170 is called a "register file" because it's more likely to be used for holding registers within a CPU core than as memory outside one. Functionally, though, if one opened up a 2600, used a 74138 to decode read and write addresses in the range $00-$7F, and threw in a 74170 (tying both sets of data pins to D0-D3, and both sets of address pins to A0-A1), the effect would be to add four nybbles of RAM to the 2600. Too small a quantity to be useful for much, but RAM nonetheless.

 

BTW, how do you fit PB bankswitching into a "standard" PLD? A CPLD like the XC9536XL would have no problem, but the smallest PLD I would expect to be usable would be a 26V12, and those have been largely superceded by CPLD's.

 

At minimum you need 13 address inputs, a timing input, a chip-select output, a timing output, and nine banking outputs (use tri-stating to select among them, and pullups to establish a default). So 14 inputs and 11 outputs.

You could reduce the number of inputs needed by using diodes to perform some of the ANDing of the address inputs, and a transistor to act as the inverter for the chip select, then you may be able to get down to a 22V10.

[Kroko]

What is a RAM, if not a collection of registers which is addressable for both reading and writing?

Lets say it like this: If anybody woud ask me about 2600 bankswitching modes and ask if F8,F6,F4 or E0 required RAM, I would still say: no it doesn't. Would you say yes ? I don't doubt that a register is a storage element, but I don't call a chip RAM just because it can somehow be used to store information. To close this discussion lets summarize it like this: cats are more tolerant with regard to what is called a RAM chip than krokodiles

 

BTW, how do you fit PB bankswitching into a "standard" PLD? A CPLD like the XC9536XL would have no problem, but the smallest PLD I would expect to be usable would be a 26V12, and those have been largely superceded by CPLD's.At minimum you need 13 address inputs, a timing input, a chip-select output, a timing output, and nine banking outputs (use tri-stating to select among them, and pullups to establish a default). So 14 inputs and 11 outputs.

Maybe I should have said: Standard Programmable Logic chip. I didn't have in mind a certain chip type. The point was, that no RAM chip is required. Its not important if you do it with a XC9536XL or a 26V12. I am sure nobody would put a RAM chip on board (at least not if you take the krokodile definition of RAM chip )

[supercat]

You could reduce the number of inputs needed by using diodes to perform some of the ANDing of the address inputs, and a transistor to act as the inverter for the chip select, then you may be able to get down to a 22V10

 

Yeah, I guess that would probably do it pretty well. BTW, I came up with an 8K bank-switch design awhile ago that could be implemented using two 7400's, a resistor, and a deglitching cap. Surprised nobody did such a thing back in the day though 3F comes pretty close. Another approach would be to use a 4066, probably four resistors, and a cap; not sure if they had 4066's back then, though.

 

I wonder how many bipolar transistors would be needed to do an 8K bankswitch cart with no logic chips (other than the EEPROM itself).

[supercat]

Lets say it like this: If anybody woud ask me about 2600 bankswitching modes and ask if F8,F6,F4 or E0 required RAM, I would still say: no it doesn't. Would you say yes ? I don't doubt that a register is a storage element, but I don't call a chip RAM just because it can somehow be used to store information. To close this discussion lets summarize it like this: cats are more tolerant with regard to what is called a RAM chip than krokodiles

 

Small RAMs are used for a variety of purposes other than providing addressable storage to a microprocessor. A number of display devices have used RAM to hold display palettes. The PCjr/Tandy 1000 used a 16x4 RAM; the EGA used 64x6; the VGA used 256x18. RAMs were are also frequently used to implement hardware memory paging (before processors started using page-lookup caches); the Parker Brothers baking scheme works much the same way as some minicomputer paging systems, although those would have typically had more than four bankable regions (and thus used something like a 256x8 RAM instead of 4x4).

 

I would define a RAM as a device or subsystem with the following criteria:

 

A RAM is an array of storage cells with one or more sets of address and data inputs and outputs, and control signals therefor. Information is stored in the cells by supplying an address of those cells and the data to be stored there, and then triggering a "store" signal. Information is read from the cells by supplying the address of the cells to be read, hitting a "read" signal, and observing the data from the chip. Storing information into the RAM at a particular address has no effect other than to allow the data to be read at that same address.

 

BTW, to illustrate the interchangeability of the terms "register file" and "RAM", the early PIC data books referred to the chips not as having any RAM, but as having 25 "registers". Later data sheets refer to them as having 25 bytes of RAM.

 

The point was, that no RAM chip is required. Its not important if you do it with a XC9536XL or a 26V12. I am sure nobody would put a RAM chip on board (at least not if you take the krokodile definition of RAM chip )

 

Functionally, it is necessary to have a chip which will perform two functions:

 

-1- Store the contents three input pints into one of three sets of latches, based upon a supplied address.

 

-2- Retrieve the contents of those sets of latches onto three output pins, based upon a supplied address.

 

A device with that functionality, however implemented, could be wired onto a microprocessor bus and used to add another nine bits of RAM (three bits addressable at each of three addresses).

[Kroko]

The Parker Brothers baking scheme works much the same way as some minicomputer paging systems

As I see it it is just storing a few bank numbers in a few registers. Just like F8,F6,F4 and any other banking scheme.

It is confusing for most people if you tell them that E0 was a bs mode which requires a RAM chip, because it is Superchip, FA, E7,AR etc.. which actually do require RAM. F8,F6,F4,3F,F0 and E0 don't.

[supercat]

It is confusing for most people if you tell them that E0 was a bs mode which requires a RAM chip, because it is Superchip, FA, E7,AR etc.. which actually do require RAM. F8,F6,F4,3F,F0 and E0 don't.

 

I can see your point in that regard. Perhaps the best terminology for SuperChip, RAM-plus, etc. would be "supplemental RAM"? The E0 bankswitching certainly does not add supplemental RAM, regardless of whether or not a RAM chip happens to be used in its implementation.

[CPUWIZ]

At minimum you need 13 address inputs, a timing input, a chip-select output, a timing output, and nine banking outputs (use tri-stating to select among them, and pullups to establish a default). So 14 inputs and 11 outputs.

 

I wonder how Parker did it with a 22pin chip.

 

http://www.atariage.com/cart_page.html?SoftwareLabelID=1955

[Kroko]

At minimum you need 13 address inputs, a timing input, a chip-select output, a timing output, and nine banking outputs (use tri-stating to select among them, and pullups to establish a default). So 14 inputs and 11 outputs.

 

I wonder how Parker did it with a 22pin chip.

 

http://www.atariage.com/cart_page.html?SoftwareLabelID=1955

I almost agree with supercat, apart from the 9 banking outputs. I think 3 are sufficient. The 3 outputs control A10 to A12 on the Rom chip. In addition PB could skip the 2 lines for the timing circuitry, because it is contained in the custom chip.