+playsoft Posted April 16, 2023 Share Posted April 16, 2023 On 4/6/2023 at 4:20 PM, SainT said: devices with 1MB of RAM (7800GD, DF, etc) Just to clarify that the DragonFly cart can support a full 1MB ROM + RAM image and runs the original BadApple demo OK. Practically speaking, anyone creating a 1MB + RAM image probably doesn't need every single bank and can leave the last switchable bank empty so that it runs on the GD. 1 Quote Link to comment Share on other sites More sharing options...
SainT Posted April 16, 2023 Share Posted April 16, 2023 32 minutes ago, playsoft said: Just to clarify that the DragonFly cart can support a full 1MB ROM + RAM image and runs the original BadApple demo OK. Practically speaking, anyone creating a 1MB + RAM image probably doesn't need every single bank and can leave the last switchable bank empty so that it runs on the GD. Is the DF 1mb + extra ram? I had assumed (possibly incorrectly?) that it was just 1mb and it had used a page from the 1mb rom area for the ram at 4000. I just wanted to standardise which page would be left for ram use rather than leave it floating. 1 Quote Link to comment Share on other sites More sharing options...
+playsoft Posted April 16, 2023 Share Posted April 16, 2023 1 hour ago, SainT said: Is the DF 1mb + extra ram? Yes, I think has 1MB plus 32K RAM (like banked RAM except that you switch it at $FFFF). 1 Quote Link to comment Share on other sites More sharing options...
Eagle Posted April 16, 2023 Share Posted April 16, 2023 Yes. 1MB+ 2x16KB Ram. Hotspot for swapping between ram banks it’s $FFFF bit D0=0 first bank D0=1 second bank. This same as SN Cart. 2 Quote Link to comment Share on other sites More sharing options...
SainT Posted April 16, 2023 Share Posted April 16, 2023 Good to know! Thanks for the clarification. Quote Link to comment Share on other sites More sharing options...
SainT Posted April 23, 2023 Share Posted April 23, 2023 A couple more requests for header flag additions : TV type details: bit 2 = 0:single region, 1:multi-region For physical hardware the user can be warned if the incorrect region of ROM is trying to be run with the current header, but for more recent multi-region ROMs there will always be one (usually PAL) region which will get an incorrect warning. Having a multi region flag will be useful to remove this warning. The PAL/NTSC flag could then be used as a preferred region for emulators. Controller type byte details: 12 = Mega7800 For the 7800GD I can use this to switch to an alternate break method and allow homebrew to use the majority of the megadrive pad buttons for their own purposes. I will reserve the mode button in combination with other buttons to activate GD related features. 4 Quote Link to comment Share on other sites More sharing options...
RevEng Posted April 24, 2023 Share Posted April 24, 2023 Sounds good to me. I should be able to take on the assembly header and 7800header updates this weekend. 4 Quote Link to comment Share on other sites More sharing options...
SainT Posted April 25, 2023 Share Posted April 25, 2023 8 hours ago, RevEng said: Sounds good to me. I should be able to take on the assembly header and 7800header updates this weekend. Much appreciated, thank-you! 😄 3 Quote Link to comment Share on other sites More sharing options...
RevEng Posted April 30, 2023 Share Posted April 30, 2023 Heads up that I've updated the assembly header and 7800header with the multi-region flag and mega7800 controls. 3 1 Quote Link to comment Share on other sites More sharing options...
SainT Posted June 8, 2023 Share Posted June 8, 2023 I'm adding the ADPCM streamed audio functionality I developed for Rikki and Vikki as a stand-alone audio feature. To enable it use bit 5 of the audio mapper field. It adds a command register at $420 to allow you to control the playback, pause and volume of ADPCM encoded audio tracks. It currently only cohabits with the TIA for audio mixing, but there's no reason not to allow all other combinations of POKEY, YM, TIA, etc... other than I'm running very very low on FPGA space. I have a 7800GD / Mega7800 features sample ROM with source which will be added to GitHub as a demonstration of how to use everything in your own games and it should all be integrated into 7800basic in due course. I've updated the header detail post to include this information: @RevEng if you wouldn't mind doing the honors on the 7800header code to add the extra feature set bit when you get a chance, please! The only limit is this feature doesn't cohabit with the Souper Mapper. It basically implements the same functionality but at a different address space to allow more modular use. 5 Quote Link to comment Share on other sites More sharing options...
RevEng Posted June 11, 2023 Share Posted June 11, 2023 On 6/8/2023 at 9:00 AM, SainT said: @RevEng if you wouldn't mind doing the honors on the 7800header code to add the extra feature set bit when you get a chance, please! The only limit is this feature doesn't cohabit with the Souper Mapper. It basically implements the same functionality but at a different address space to allow more modular use. I've added the adpcm@420 flag to 7800header, and added a corresponding comment to the a78_asm_header file. 1 1 Quote Link to comment Share on other sites More sharing options...
SainT Posted June 11, 2023 Share Posted June 11, 2023 Awesome, thank-you! 2 Quote Link to comment Share on other sites More sharing options...
+Pat Brady Posted July 24, 2023 Share Posted July 24, 2023 I know mram@4000 is mirror RAM a la Rescue on Fractalus. What's the difference between ram@4000 and hram@4000? Quote Link to comment Share on other sites More sharing options...
RevEng Posted July 25, 2023 Share Posted July 25, 2023 hram is "halt-banked ram". Presently it's just implemented in banksets. 2 1 Quote Link to comment Share on other sites More sharing options...
Eagle Posted August 1, 2023 Share Posted August 1, 2023 Quote ; bit 3 ; YM2151 @ $0461 - $0462 Hmm 🤔 Quote Link to comment Share on other sites More sharing options...
SainT Posted August 1, 2023 Share Posted August 1, 2023 (edited) 10 minutes ago, Eagle said: Hmm 🤔 ? $460 is the base address. Same as all the other listed devices? Actually I’m not sure where that quote is from now! I thought it was edited from my header post, now I’m not so sure… 😆 Never mind, I see it’s from the 7800 header asm, I see your point! 😆 Edited August 1, 2023 by SainT 1 Quote Link to comment Share on other sites More sharing options...
Eagle Posted August 1, 2023 Share Posted August 1, 2023 14 minutes ago, SainT said: Never mind, I see it’s from the 7800 header asm, I see your point! 😆 Yes. I was confused and had to check my code Line 69, 126 need correction. Quote Link to comment Share on other sites More sharing options...
RevEng Posted August 1, 2023 Share Posted August 1, 2023 Oh dear. Seems like off-by-one errors have now crept into my documentation. Fixed now. 3 1 Quote Link to comment Share on other sites More sharing options...
Eagle Posted September 3, 2023 Share Posted September 3, 2023 (edited) Slowly I need to book some space for SN and SN2 cart before we move further. Also we need bit for our SN cart family This is already implemented in our dev MiSTer core Thanks SN Cart2 Registers POINTER_BASE equ $400 MEM0DATA equ POINTER_BASE ;Memory data in/out MEM1DATA equ POINTER_BASE + $01 ;Memory data in/out MEM2DATA equ POINTER_BASE + $02 ;Memory data in/out MEM3DATA equ POINTER_BASE + $03 ;Memory data in/out MEM1ADR0 equ POINTER_BASE + $04 ;Memory address 0 MEM1ADR1 equ POINTER_BASE + $05 ;Memory address 1 MEM1ADR2 equ POINTER_BASE + $06 ;Memory address 2 MEM1ADR3 equ POINTER_BASE + $07 ;Memory address 3 MEM2ADR0 equ POINTER_BASE + $08 ;Memory address 0 MEM2ADR1 equ POINTER_BASE + $09 ;Memory address 1 MEM2ADR2 equ POINTER_BASE + $0A ;Memory address 2 MEM2ADR3 equ POINTER_BASE + $0B ;Memory address 3 MEM3ADR0 equ POINTER_BASE + $0C ;Memory address 0 MEM3ADR1 equ POINTER_BASE + $0D ;Memory address 1 MEM3ADR2 equ POINTER_BASE + $0E ;Memory address 2 MEM3ADR3 equ POINTER_BASE + $0F ;Memory address 3 MEM0ADR0 equ POINTER_BASE + $10 ;Memory address 0 MEM0ADR1 equ POINTER_BASE + $11 ;Memory address 1 MEM0ADR2 equ POINTER_BASE + $12 ;Memory address 2 MEM0ADR3 equ POINTER_BASE + $13 ;Memory address 3 MEM0INC equ POINTER_BASE + $14 ;Memory address increment MEM1INC equ POINTER_BASE + $15 ;Memory address increment MEM2INC equ POINTER_BASE + $16 ;Memory address increment MEM3INC equ POINTER_BASE + $17 ;Memory address increment MEM0DEC equ POINTER_BASE + $18 ;Memory address decrement MEM1DEC equ POINTER_BASE + $19 ;Memory address decrement MEM2DEC equ POINTER_BASE + $1A ;Memory address decrement MEM3DEC equ POINTER_BASE + $1B ;Memory address decrement SN76489 equ $43F SN76489dual equ $43E ; FPGA VGM player for YM2151, YM2612, SN76489 VGMREG equ $462; -- register number VGMPlayer VGMDAT equ $463; -- read/write register VGMPlayer ;VGMREG ;$00 - vgm_control - bit7 = on/off play, bit6 = on/off loop ;$01 - $04 - 32bit vgm_play_address (to vgmdat) ;$05 - $08 - 32bit vgm_loop_address (to vgmdat) YM2612BASE equ $464 ;($464-$467) MemReg equ $FFFF ;bit 0 - lower/upper 16KB ram, bit 1 - mirror ram A8, bit 2 - mirror ram A9, bit 3 - reserved, bit 4 - mirror A8/A9 only for lower 8KB ram ;************* 4KB banks* *********************** $8000 -> write 0-255 (select 4KB bank from 0-255) $9000 -> write 0-255 (select 4KB bank from 0-255) $A000 -> write 0-255 (select 4KB bank from 0-255) $B000 -> write 0-255 (select 4KB bank from 0-255) $C000 -> write 0-255 (select 4KB bank from 0-255) $D000 -> write 0-255 (select 4KB bank from 0-255) $E000 -> write 0-255 (select 4KB bank from 0-255) $Fxxx - it's fix Edited September 3, 2023 by Eagle 1 Quote Link to comment Share on other sites More sharing options...
RevEng Posted September 3, 2023 Share Posted September 3, 2023 The standard we've hashed out in the past was to officially allocate mappers when there is either a released game, or a prerelease game with final hardware prototyped and release is imminent. For dev purposes you can just self-assign a mapper index in the v4 header. (N.B. We don't have any v3 header bits left.) 1 Quote Link to comment Share on other sites More sharing options...
DanBoris Posted September 5, 2023 Share Posted September 5, 2023 On 9/3/2023 at 5:07 PM, RevEng said: The standard we've hashed out in the past was to officially allocate mappers when there is either a released game, or a prerelease game with final hardware prototyped and release is imminent. For dev purposes you can just self-assign a mapper index in the v4 header. (N.B. We don't have any v3 header bits left.) ... and I thought 16 bits would be plenty. Quote Link to comment Share on other sites More sharing options...
RevEng Posted September 5, 2023 Share Posted September 5, 2023 5 hours ago, DanBoris said: ... and I thought 16 bits would be plenty. Yep. I guess it's a good problem to have. Lots of hardware development going on, on our little platform. 1 Quote Link to comment Share on other sites More sharing options...
Aking Posted March 25 Share Posted March 25 hi everyone, i can't seem to "unfix" embedded size and unsync v3+v4 help? Quote Link to comment Share on other sites More sharing options...
RevEng Posted March 25 Share Posted March 25 6 hours ago, Aking said: i can't seem to "unfix" embedded size and unsync v3+v4 I'm not really sure why you'd want to do that... the embedded size needs to be correct, and v3+v4 headers should be synced for maximum compatibility with emulators and flash devices. Older emulators will ignore any v4 headers present, if they don't support them. That said, if you want to go back to what you had before, 7800header always creates a ".backup" version of your rom. (though if you made changes in two or more sessions, the backup will be overwritten) Quote Link to comment Share on other sites More sharing options...
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