Small comparision

[+bob1200xl]

The one advantage of the 65816 is that it runs 6502 code at the same time as providing 24 bit addressing into memory. You can just drop it into an XL and run virually all of our existing s/w.

 

All the 6502 addressing modes are supported as 24-bit. If that isn't optimal, blame the 6502, not the 65816.

 

Bob

 

 

 

Just pointing out to Bob how poor the 65816's 24 bit support is compared to a real 16 bitter.

It may support 24 bit addressing but the differences are pretty glaring.

<edit>

The limitations actually leave it with little advantage over another 8 bit + MMU.

[JamesD]

Actually, I forgot the 65816 added stack relative addressing.

So you don't have to copy the stack pointer to page zero or an index register to access parameters on the stack.

That would drop several instructions from a C subroutine.

 

ADC, AND, CMP, EOR, ORA, SBC, LDA, and STA can all be used with stack relative addressing.

Everything goes through A though so no LDX, LDY.

 

So the code would look more like this. My syntax is probably off a bit.

;set 8 bit mode here (not looking up how at the moment)
LDA	HSource,S ; high byte of source address
STA	Move+1	 ; modify hi byte of source address passed to MVN
LDA	HDest,S
STA	Move+2   ;modify hi byte of dest address passed to MVN
;set A to 16 bit mode here
LDA	Source,S
TAX
LDA	Dest,S
TAY
LDA	Length,S
Move:
MVN	HiSrc,HiDest ;hi bytes are modified in the code above

So at least 12 instructions but definitely an improvement over non-stack relative code.

Keep in mind that still leaves out some stack handling operations, doesn't handle moves exceeding 16 bits, and leaves out the return.

 

If you were only operating in 64K, you could have the hi bytes in the MVN set to zero and skip self modifying code.

So when used more like an 8 bit CPU, it works pretty well and looks something like this. Again, my syntax may be off.

;set A to 16 bit mode here
LDA	Source,S
TAX
LDA	Dest,S
TAY
LDA	Length,S
Move:
MVN 0,0

[JamesD]

The one advantage of the 65816 is that it runs 6502 code at the same time as providing 24 bit addressing into memory. You can just drop it into an XL and run virually all of our existing s/w.

And? What does that have to do with what the point I was making?

It sounds like you are just defending the chip for the sake of defending the chip and ignoring my point.

 

All the 6502 addressing modes are supported as 24-bit. If that isn't optimal, blame the 6502, not the 65816.

 

Bob

I'm going to disagree here.

There were several things that would have made the 65816 easier to use that were left out that can't be blamed on the 6502.

 

One example... the stack relative addressing only supports A. The 65c02 had already added instructions for pushing/pulling X,Y to/from the stack. This is almost a step backwards. At the very least, I think LDX, LDY, STX, STY, all should have had stack relative addressing and that's just for starters. 24 bit addressing didn't need to require the same type of restrictions as 16 bit addressing did on the 6502.

<edit>

BTW, look at how you use the new B register when A is in 8 bit mode.

<edit>

Code for setting 8 or 16 bit mode.

If you know for certain the carry will be set or clear, then you can skip the SEC or CLC.

Since carry isn't altered by LDA or STA, the memcpy code would require 2 instructions for each mode change.

; set 8 bit mode
SEC
XCE
; set 16 bit mode
CLC
XCE

The 8/16 bit mode should have always been switchable with 1 instruction.

Edited December 27, 2011 by JamesD

[potatohead]

IMHO, there is no blame, just implementations.

 

When I look at the moto chips, 6809 and 68K, the thought that went into them is amazing. The 09 as good as it is, was improved by Hitachi, suggesting there is almost always some better implementation to be had. 65816 is convoluted. Just got done looking at it. Frankly, lots of chips are convoluted. Sometimes a great performance drops outta that, often though, we just learn where the tricks are and the thing does what it does well.

 

Honestly, I suspect "plug the hole" kind of thinking went into the '816, where a more holistic approach went into the moto stuff. That's the core difference right there.

 

As for defend the chip! Well, we like what we like. That's where the fun is, no harm in that.

Edited December 27, 2011 by potatohead

[+bob1200xl]

I don't know the point you are making or I would not ignore it... I told you, I'm not a programmer - I'm a hardware guy.

 

The 6502 comes with a set of instructions. If you are going to expand that existing set into 24-bit addressing and such, you consume the remaining available opcodes, don't you? You cannot just toss them all out and start over.

 

Yes, I am defending the chip. It is a viable and useful enhancement to 6502 systems. You should get one and find out what's good about it!

 

Bob

 

 

 

The one advantage of the 65816 is that it runs 6502 code at the same time as providing 24 bit addressing into memory. You can just drop it into an XL and run virually all of our existing s/w.

And? What does that have to do with what the point I was making?

It sounds like you are just defending the chip for the sake of defending the chip and ignoring my point.

 

All the 6502 addressing modes are supported as 24-bit. If that isn't optimal, blame the 6502, not the 65816.

 

Bob

I'm going to disagree here.

There were several things that would have made the 65816 easier to use that were left out that can't be blamed on the 6502.

 

One example... the stack relative addressing only supports A. The 65c02 had already added instructions for pushing/pulling X,Y to/from the stack. This is almost a step backwards. At the very least, I think LDX, LDY, STX, STY, all should have had stack relative addressing and that's just for starters. 24 bit addressing didn't need to require the same type of restrictions as 16 bit addressing did on the 6502.

<edit>

BTW, look at how you use the new B register when A is in 8 bit mode.

[potatohead]

I wouldn't mind putting one in my Apple. I know that can work, particularly the pin compatible one. Is that still available? Read about people doing that before. What are people stuffing in Ataris? Same thing? What about XL / XE as opposed to the 400 / 800?

 

The dream chip for me would be a 6809 though. Always thought it would rock hard to have the A8 chipset able to do what it does without actually stopping the CPU like it currently does. The Moto chips were built with that in mind, and Woz figured out the '02 would do it, just so long as one was careful...

[JamesD]

I wouldn't mind putting one in my Apple. I know that can work, particularly the pin compatible one. Is that still available? Read about people doing that before. What are people stuffing in Ataris? Same thing? What about XL / XE as opposed to the 400 / 800?

The 65802 has been long gone. I tried buying one back in the 90's in case I ever bought an Apple II and they were already gone by then, snapped up by Apple owners for the most part.

 

Since the the Atari uses the 6502C, I don't know if it would just plug in anyway. If you search the net you'll find people have designed adapters to hook the 65816 to the 6502 socket (the 65816 requires some different signals). It seems to work on the C64 but when tried on the Oric... the odd buss timing caused complications and I'm not sure they have been resolved yet.

I think it would work ok on the Atari if you account for any differences between the 6502C and 6502, I really don't know for sure.

 

The dream chip for me would be a 6809 though. Always thought it would rock hard to have the A8 chipset able to do what it does without actually stopping the CPU like it currently does. The Moto chips were built with that in mind, and Woz figured out the '02 would do it, just so long as one was careful...

Well, the 6809 was designed with software in mind. If I remember right, Motorola did a lot of code profiling on existing 6800 code and sat down to figure out where the bottlenecks were and how to eliminated them. They did an amazing job.

[+bob1200xl]

I assume that you are referring to DMA from ANTIC? You could 'share' the memory bus between ANTIC and the CPU since the first half of the bus cycle is pretty much a NOP, but it takes less hardware and gives better results to just crank up the CPU clock to 7.16MHZ.

 

Bob

 

 

I wouldn't mind putting one in my Apple. I know that can work, particularly the pin compatible one. Is that still available? Read about people doing that before. What are people stuffing in Ataris? Same thing? What about XL / XE as opposed to the 400 / 800?

 

The dream chip for me would be a 6809 though. Always thought it would rock hard to have the A8 chipset able to do what it does without actually stopping the CPU like it currently does. The Moto chips were built with that in mind, and Woz figured out the '02 would do it, just so long as one was careful...

[JamesD]

The 6502 comes with a set of instructions. If you are going to expand that existing set into 24-bit addressing and such, you consume the remaining available opcodes, don't you? You cannot just toss them all out and start over.

Well, the 65816 added more address modes through new opcodes, but for the most part it looks as though things were tacked on to existing instructions through mode switching and page registers. And the new address modes appear to be tacked on to existing address modes as well. There is still room for more instructions.

While this is logical to a hardware designer, the end result is awkward from a programming standpoint.

 

I think some careful code analysis might have caused them to make some different choices.

 

Yes, I am defending the chip. It is a viable and useful enhancement to 6502 systems. You should get one and find out what's good about it!

 

Bob

The 65816 is a big improvement over the 6502 but only with new code. You can alter existing code to take advantage of the new features though... but it will only run on other machines with a 65816.

 

I have a IIgs and have messed around in C a bit. The compiler output is a bit ugly but better than for the 6502.

I just need to spend more time with it in assembly.

[JamesD]

The music was generated separate from the texture mapped demo, but at 4MHz, both might be possible at the same time. It might even run a little faster.

At 8MHz, it should make a very playable game. I need to finish setting up my new Terasic DE1 board so I can get CoCo 3 FPGA running.

Edited January 9, 2012 by JamesD

[JamesD]

The music was generated separate from the texture mapped demo, but at 4MHz, both might be possible at the same time. It might even run a little faster.

At 8MHz, it should make a very playable game. I need to finish setting up my new Terasic DE1 board so I can get CoCo 3 FPGA running.

[emkay]

The music was generated separate from the texture mapped demo, but at 4MHz, both might be possible at the same time. It might even run a little faster.

At 8MHz, it should make a very playable game. I need to finish setting up my new Terasic DE1 board so I can get CoCo 3 FPGA running.

http://www.youtube.com/watch?v=W-Ba2X_AZrI

 

Haven't seen this yet.

But imagine, the A8 has it's way to go there... Gr.9 with 4x4(8x8) pixel ... POKEY is playing the higher notes, low channel is built on digitizing.

[JamesD]

That appears to be a 16 color graphics mode but I'm not sure if the screen width is set to 320 or 256. I'm thinking 320.

[potatohead]

Me too. Damn cool, BTW.

[JamesD]

From the CoCo page on facebook:

According to the creator:" My 'Wolf-3d' raycaster runs in 256x192, but the effective horizontal resolution is 128 pix since I always output a byte at a time. Essentially it is 128x192"

[potatohead]

Are the pixels seen noise then? CoCo 3 computers can get a bit noisy, but I didn't think that much could be seen.

[JamesD]

I think he's just duplicating the pixel data in the top and bottom nibble of the byte.

<edit>

That explains the blocky look of the texture mapped walls, but I notice that the resolution is better where the walls and floor meet so not everything is done that way.

Edited January 11, 2012 by JamesD

[JamesD]

Raycasting on the MSX Turbo R

http://www.youtube.com/watch?v=DJDqe8fP9qE

 

BTW, I found out that the 64180 was used in a commercial machine.

JVC used it in one of their MSX machines, the HC-95.

The HC-95 had a standard clocked Z80 and the 64180 clocked at just over 6MHz.

The HC-95 came out in '85 or '86 (depending on what web page you listen to).

<edit>

Apparently the HC-90 also had the 64180.

Edited January 15, 2012 by JamesD

[JamesD]

<edit> wrong thread

Edited January 16, 2012 by JamesD