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I've done some timing analysis on a couple TIAs.


Bryan

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I can believe there are glitch issues with some 2600s after looking at a TIA I have here:

 

Synertek C010444D-03 8114D

 

The phi0 clock out of TIA has a ~60/40 duty cycle and phi2 is falling a little before the falling edge of OSC (although this will be 6507 dependent). This is out of spec according to the datasheet although I haven't seen any game issues. I think the main problem is skewed clocks causing a race condition where changes happen a cycle early.

 

Anyway, I've been messing with interfacing some programmable logic to a 2600 and it wouldn't have worked if I'd relied on the original timing specs. I wonder how bad the "problem" TIAs are.

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Yes. Normally, updates to registers take effect on the first pixel after the CPU write cycle (after R_W goes high), but if the duty cycle of the phi0 clock is off, the register update can take effect one pixel early. Atari was sloppy with their delays (or at least they needed better QC from their chip fabs). A small external circuit could generate a better phi0 and would probably fix the problem.

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