ROL ZP bus timing - logic analyzer results

[ZackAttack]

I've been researching how to perform quad bus stuffing with the harmony. Thought I'd share some of my analysis of the VCS bus timing in case anyone is curios what a read modify write looks like on a NTSC system. PAL would be almost identical since they only differ by 7ns per cycle. Please note that due to lack of additional logic analyzer channels only A0-A7 and D0-D7 is captured.

 

 

[+rbairos]

Can you explain what quad bus stuffing does w.r.t regular bus stuffing?
ie, what increase in average register write speed do you get in this setup?
Thanks.

 

[ZackAttack]

Regular bus stuffing involves a 3 cycle store to zeropage instruction. On the thirst cycle the value placed on the data bus is overridden with the desired value. This allows a TIA register to be written to every 3 cycles as many times as you want without having to spend cycles on loading the registers with new values.

 

Quad bus stuffing involves a 5 cycle instruction that does a read modify write. Due to the implementation of the 6507 there is a dummy write on cycle 4 prior to the actual write on cycle 5. In this case both the address and data busses will be overridden on each of the write cycles giving a total of 4 stuff operations. This allows 2 TIA registers to be written to every 5 cycles.

 

Assuming a new value must be provided for each write and a 76 cycle scan line this allows greater TIA bandwidth and better graphics and sound.

No stuffing: 15 TIA writes

Bus Stuffing: 25 TIA writes

Quad stuffing: 30 TIA writes

 

In theory there could also be hex bus stuffing which would use the BRK instruction to update 3 TIA registers in 7 cycles but that would be even more difficult to implement than quad and doesn't provide any benefit. As of right now the regular single bus stuffing appears to be the only one that is feasible to implement with harmony/melody hardware.

[+SpiceWare]

With regular bus stuffing the 6507 code controls which TIA registers are written. If you want to do something like Draconian, which can reposition every object, you'll need 56 kernels to draw the screen (11 for each object to reposition it, plus 1 kernel for scanlines without a reposition).

 

With quad the hardware in the cartridge controls which register, so a single kernel would accomplish the same.

[Thomas Jentzsch]

No stuffing: 15 TIA writes

Bus Stuffing: 25 TIA writes

Quad stuffing: 30 TIA writes

 

In theory there could also be hex bus stuffing which would use the BRK instruction to update 3 TIA registers in 7 cycles but that would be even more difficult to implement than quad and doesn't provide any benefit.

I count ~2 TIA writes more with BRK (76/5*2 = 30.4 vs 76/7*2 = ~30.6). But I can see the quite large extra difficulty to implement this (if possible at all).

[ZackAttack]

Yeah if it were possible to do it with BRK I can think of one cool use for it though. Setting the background color to produce two 3 pixel wide colors every 18 pixels. Stagger this across three scan lines just like I do with the PF for my 40x64 background bitmap kernel. Since the pixels are now 3 wide instead of 4 it becomes a 53x64 bitmap.

XX____XX____XX____
__XX____XX____XX__
____XX____XX____XX

Could make for a cool FPS demo assuming it doesn't fry the VCS.

[+rbairos]

Thanks for the specific info.
Reason I ask, was I was reading up on the initial state of the 6502 on power on this morning, and noticed the 3 writes for BRK, NM, IRQ.

One thing though, what if it was an NMI or IRQ alternating with BRKs?

Unlike BRK, NMI clears the instruction register to 0 (BRK), so Im assuming one less cycle to fetch the opcode ? (every other operation)

[ZackAttack]

One thing though, what if it was an NMI or IRQ alternating with BRKs?

 

Unlike BRK, NMI clears the instruction register to 0 (BRK), so Im assuming one less cycle to fetch the opcode ? (every other operation)

 

 

 

 

They all consume the same amount of cycles. http://www.pagetable.com/?p=410

 

Also, I don't think it's possible to trigger NMI or IRQ from the cartridge since only the address and data bus pins are brought to the cartridge connector.

[+rbairos]

Right, I see
"1 PC R fetch opcode (and discard it - $00 (BRK) is forced into the opcode register instead)"
Thought it might be skipping this step entirely from the original description I found.
Good point about not being able to trigger IRQ, NMI through opcodes.

Edited November 27, 2017 by rbairos

[+nanochess]

I've learnt from this Cool!

[vidak]

This is some next-level wizardry.