+FarmerPotato Posted June 23, 2022 Author Share Posted June 23, 2022 Update: I’ve fixed the memory card, mostly. The PLD is not storing page bits. I greatly expanded MEMTEST to test XOPs, and CPU error codes. The Macrostore ROM that @pnr got from the 99110 is loaded. It correctly generates the ILLOP interrupt. I know that the page registers are stuck at all 1s, so I could rely on a program in the top page of ROM, and use the top page of RAM. Design Decisions The next PCB build will have the full memory mapper in FPGA. I’ll consolidate everything so far into one board with 2MiB of memory. (128K ROM.) The external bus will be NuBus. NuBus has completely fair arbitration. Main use for that is disk I/O doing DMA. The bus is 32 bits wide. I use 28 address bits for 256MiB. The main memory of 32 MiB will be on NuBus. The memory mapper has a reach of 256MiB, using 16 bit page registers. (User programs can only see the lower 8 bits, for a reach of 1 or 2MiB.) Each of 8 card slots gets a dedicated 1MB of address space for its DSR ROM and any port interfaces. (CRU is unified into the memory space.) DSR ROMs provide plug-n-play capability through a system much like Open Firmware. All DSRs are written in Forth. Those are the big items. I will spend a little time on the PLD bug, but move on to some actual programs. Or hook up the SD card. 6 1 Quote Link to comment Share on other sites More sharing options...
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