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Do we have the Rave99 speech adapter PAL equations?


jedimatt42

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I've mapped out the following pinout for the PAL

 

         +------+
DBIN -> (1)   (24) -- VCC
AMC  -> (2)   (23) <- MEMEN*
AMA  -> (3)   (22) -> LED*
AMB  -> (4)   (21) -> SBE
A1   -> (5)   (20) -> 74'245-DIR
A0   -> (6)   (19) -> SPCH_A5
A3   -> (7)   (18) -> SPCH_A15
A2   -> (8)   (17) -> 74'245-OE
A5   -> (9)   (16) -> RBDENA
A4   -> (10)  (15) -> READY
A15  -> (11)  (14) <- SPCH_READY (EDIT)
GND  -- (12)  (13) -- NC
         +------+

 

Edited by jedimatt42
Pin 14 is input from speech synth READY signal
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My first guess: 

 

SBE <= !MEMEN && A0..A4 == 0b10010 && !A15 && AMA..AMC == 0b111 && !(A5 && DBIN)

LED <= !SBE

SPCH_A5 <= A5

SPCH_A15 <= A15

74'245-OE <= !SBE

74'245-DIR <= DBIN

RBDENA <= !SBE

RBDENA.OE <= !SBE

READY <= This one surprises me, so probably wrong..  ( I'll pretend this is for purposes of buffering output from synth's READY )

 

It is not apparent to me why A5 is buffered through the PAL, unless it is also worked into something else... combined with DBIN for agreement? 

Edited by jedimatt42
Wisdom from FarmerPotato, also I forgot MEMEN, and RBDENA-tristate, and NAND is not the same as not-equals, and it doesn't work still.
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5 hours ago, jedimatt42 said:

 

It is not apparent to me why A5 is buffered through the PAL, unless it is also worked into something else... combined with DBIN for agreement? 

Think of read before write. SBE must not activate during a read from the write address. A5 distinguishes 9000 from 9400. Its why we have separate blocks for read and write. 
 

I wondered why WE is not in there. Guess it goes straight to the 5200?

Edited by FarmerPotato
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I can hard code the LED on ( 'b'0 ) so that works..

I think the '245 dir might be inverse of DBIN. But I'm tired, so I'll try that tomorrow.

 

If I force READY to 'b'0, I get the nice F18A init screen since no CPU written to it yet. But I have bus clash right now... 

 

Besided having forgotten A5 vs DBIN, I had forgotten the MEMEN* signal too :)  LOL...

 

getting closer.

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  • 6 months later...
On 4/12/2021 at 1:15 AM, jedimatt42 said:

I can hard code the LED on ( 'b'0 ) so that works..

I think the '245 dir might be inverse of DBIN. But I'm tired, so I'll try that tomorrow.

 

If I force READY to 'b'0, I get the nice F18A init screen since no CPU written to it yet. But I have bus clash right now... 

 

Besided having forgotten A5 vs DBIN, I had forgotten the MEMEN* signal too :)  LOL...

 

getting closer.

every get any progress on this?  I also have a Rave99 card without a PAL and one with it.  I don't think I have anything that will read the contents though.

 

 

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19 hours ago, Shift838 said:

every get any progress on this?  I also have a Rave99 card without a PAL and one with it.  I don't think I have anything that will read the contents though.

 

 

You can manually read the PAL as I did with the other ones, BUT you need a good working PAL chip and card.

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I don't have one of the PALs.

 

I had been working from a board I found some other faults with.  

 

I've just been using the design theory documented on ti-tech-pages with a metered out mapping of the socket and trying to rebuild the gap in wincupl.

 

I backlogged this to finish the year focused on ForceCommand.

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17 hours ago, dhe said:

>>Rave99 card without a PAL

 

Why would a Rave99 card not have a PAL?

I had a good card with a SNUG PAL in it. And a bad card with a 4A PAL. I put the working combo together and gifted it to someone. That left me the bad card which I believe is repaired, except the SNUG PAL doesn't work in a 4A.

 

I could probably borrow a good PAL from my pal Arcade shopper, but now I am emotionally attached to the challenge.

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15 minutes ago, Shift838 said:

can the pal be read with a TL866II-Plus?  if not what can read it.  I have a working card.

No, (if it's locked) it must be manually decoded ie: cycling all inputs and checking all outputs.

That's how I did all the others I decoded. 

Edited by Fritz442
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  • 1 month later...
48 minutes ago, Ksarul said:

That makes this card reprodicible. . .I will work on a new layout with the AMA/B/C mod on it and ask Richard Bell if he's interested in doing a run of them, since he is the current owner of the IP for the card.

If he was already the IP owner, shouldn't he already possess the knowledge represented by these files? 

 

Does he actually have possession of IP? Such as design documents? 

 

These equations and the boards in hand that I've seen already account for AMA/B/C... Are you talking about the further GENMOD decoding of AMD/E? 

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When Rave99 closed their doors, Cecure Electronics obtained the rights to the Rave99 products. When Cecure closed up shop, they sold their entire remaining stock and the rights to it to Richard Bell. Unfortunately, one of the storage units containing a lot of the stock/documents Richard purchased was impounded and cleared out by the storage unit owner because of some issues with the storage payments (IIRC). A lot of stuff was lost in that transfer. Cecure had the PAL equations, as they did at least one run of the boards sometime around 1995 or so. I know Richard has some programmed PALs, he may also have the necessary JEDEC files buried in the mass of things he received from Cecure. Having this set in the wild serves two purposes--it allows folks to repair the one part of the card that wasn't readily available and it gives me the last puzzle piece I needed to make a new board layout for Richard.

 

As to the decoding, adding AMD/E would be a good idea to enhance compatibility. . .

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Well, I don't have a G20V8 on hand, but I have a G22V10, which I've been able to program from Fred's TISPEECH.EQN after translating it to WinCUPL, and it partially works. 

 

I had to tristate the RDYO signal out of the GAL to the PEB BUS. I'm setting it to high impedance unless SBE is high. That doesn't seem 100% correct yet though. I can run Parsec and Bigfoot and my gcc example for playing a speech sample... but both XB CALL SAY and fbForth SAY using the ROM vocabulary fails with garbled sound, and sometimes hangs. 

 

I do have some GAL20V8's on a boat... 

 

 

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  • 2 weeks later...
On 12/23/2021 at 11:50 PM, Fritz442 said:

Basically, pin 15 was not in a high-impedance state like pin 16 was.

Input pin 14 was ok, so pin 15 was the issue.

It was a long time ago I did this. I see on that particular Rave PCB that pin 14 and 15 of the GAL are not connected to the PCB but pin 14 and 15 on the PCB are shorted. I can't remember what the issue was here.

 

I suppose that this

    RDYO          = RDYI * SBE

    RDYO.trst    = !RDYI + !SBE

 

will solve that. New knowlegde after 27 years !!

IMG_0304.JPG

IMG_0305.JPG

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I'm surprised you need to consider the SBE signal on the RDY logic... 

 

There is a pull-up in the GAL on RDYI, so it is provided LOW or high-impedance (which the GAL drives to HIGH internally) 

So I would think the equivalent to the solder bridge would have been more simply:

 

RDYO = 'b'0

RDYO.trst = !RDYI

 

I think this is the language Fred was using: https://archive.org/details/bitsavers_mmipalasmpeJul87_18634780/page/n87/mode/2up )

 

If the synthesizer is asserting ready-LOW then output LOW, otherwise hold high-impedance. 

 

What am I missing? Is the SBE term necessary, or is it optimizing so that the CPU can continue to access anything but the speech while the synth asserts ready-LOW? 

 

(I'm not saying my suggestion works, I'm saying I want to learn more)

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