SIO protocol

[ijor]

Nyquist always applies.

 

It doesn't apply for synchronous transmissions.

 

There are plenty devices that transfer a their exact clock frequency. Consider one edge-triggered flip-flop on each end, both clocked by the same clock signal. I'm sure you agree that a matched pair of flip-flops can trasmit and receive at 1 bit per cycle, don't you?

 

Of course, for implementing this, the flip-flop on the receiver must be actually clocked by the serial clock. You might also need to do phase shifting, or send at one edge and receive on the other in the worst case.

 

There is still a question if Pokey uses the serial clock as the actual flip-flop clock or not (and I claim it does not). But if it does, then certainly you wouldn't need a 2x clock to sample rate.

Edited February 13, 2009 by ijor

[ijor]

ijor: pretty sure of that, i use the same setup for reading serial eeproms (8mbit or more) so it had to be fast for starters

and as i said, above that pokey will start making errors - not often, but it will

 

I wasn't implying that instead of 1 MHz you were transferring slow (say, at 1 KHz). And I never said you can't do it fast. The only question is how fast.

 

May I ask you why are sure you were clocking Pokey at 1 MHz? Did you use a scope or some instrument? What kind of hardware you were using to generate the clock and the signals? Was you measuring the time on the PC or on dedicated hardware?

 

Also, don't you find it a bit strange that it works only upto 1 MHz? 1 MHz doesn't sound as any magic number related to Pokey or the A8.

 

Lastly, can you explain why you had to send 10 bits of zeros when a bit was missed?

 

i think 895khz (or whatever phi2/2 is) should be treated as safe max speed for pokey

 

There is a world of difference between 1 Mhz and PHI2/2. Not in terms of speed, perhaps. But yes in terms of that it would make much more sense as a magic number.

[+poobah]

Nyquist always applies.

 

It doesn't apply for synchronous transmissions.

 

There are plenty devices that transfer a their exact clock frequency. Consider one edge-triggered flip-flop on each end, both clocked by the same clock signal. I'm sure you agree that a matched pair of flip-flops can trasmit and receive at 1 bit per cycle, don't you?

 

Of course, for implementing this, the flip-flop on the receiver must be actually clocked by the serial clock. You might also need to do phase shifting, or send at one edge and receive on the other in the worst case.

 

There is still a question if Pokey uses the serial clock as the actual flip-flop clock or not (and I claim it does not). But if it does, then certainly you wouldn't need a 2x clock to sample rate.

I'll just stop at the "both clocked by the same clock signal" part

the clock signal 'counts' as samples.

Information Theory is pretty clear on this one.

 

but that's a side note to the pokey thing. there's no phase locked clock involved here, so you can't do 1 bit per cycle, and even if there were, there's still internal delays (as you noted).

 

interesting stuff tho.

[candle]

bad phoobah!

 

ijor: if pokey will miss a bit, and valid start bit was received, then anything that follows must be a byte, so if pokey skipped one bit, stop bit will count as information bit, start bit will become stop bit, and for start bit you will get an arbitrary bit matching start pattern, thus sending 10 bits of zeroes make things reset and aligned again

and i know the speed because i've used the same delay loops that i have used for spi-flash memory devices, and those were measured by time whole memory was read

if you need a readout from the scope it can be arranged, but what for really? for me it isn't the max speed important, but anything that will allow transferring faster and more reliably than at this time

rs232 is becoming more and more obsolete in novadays pc, and thus - need to get it out the equasion.

usb port seem the right choice

i just don't want to stick to 19200 presently obtainable by means of rs232 usb converters, and i can't afford atarimax sio2pc usb and even if i could - why? this is the same ft232 chip with gal with logic for prosystem, there is nothing more there, but smoke and mirrors

Edited February 13, 2009 by candle

[atariksi]

I wasn't making fun of you-- I was pointing out how by being vague or unclear about something does not allow one to draw an exact conclusion.

 

I didn't reach any (technical) conclusion. My only conclusion when I made that sentence, was that we have a hard time understanding each other.

 

You mentioned overclocking in post #55. Okay, so if there's no relationship between bi-dir clocking modes and internally clocked modes, then you can't state I am taking POKEY beyond its spec. by doing >1mbit/second transfers.

 

I did mention overclocking, but I didnt' say you are or were overclocking at 1.79 MHz. I was trying to explain my point, and I mentioned what it might happen if you would overclock Pokey (say, at 3 MHz). Please read that paragraph again and may be you would be able to understand what I was trying to say.

 

I didn't say anything at all regarding Pokey specifications. There are no such specifications AFAIK. I mean, AFAIK nowhere it is specificied which is the maximum Pokey serial rate.

 

I didn't read anything about 3Mhz or > 1.79Mhz in your sentence; it implied greater than internal serial rate would be overclocking since that was also under discussion. Maximum internally clocked serial rate is 127kbits/second. Since I already have done 333kbs perfectly using external clock, without removing any capacitors, or any other hardware mods, I knew you were wrong.

[atariksi]

and let us not forget our good ol' friend nyquist.....

 

If you can lock into the phase of the signal coming in (know the phase), Nyquist's theory of sampling >=2X does not apply. So in this case since you know the POKEY frequency and transmitters frequency and if you synch up the phase properly intially, you don't need POKEY to be doing >=2X sampling of input.

 

Nyquist always applies. "knowing" the phase of the incoming signal involves obtaining information from the signal (those are samples).

but that's theoretical nit picking.

 

How do you plan to "lock into the phase of the signal coming in" to pokey?

 

It depends on the application and hardware setup. A simple example is the way modems work-- they lock into the start bit and then run at the same baud rate as the sender. Atari OS locks into the baud rate of the cassette player by calibrating the intial header bytes of 0x55. If you can't lock into the phase, you would need to sample >=2X. Now in POKEYs case of internally clocked data, you only have to get it precise enough to receive 9 bits + start bit since you would resync at the next start bit.

[HiassofT]

i just don't want to stick to 19200 presently obtainable by means of rs232 usb converters, and i can't afford atarimax sio2pc usb and even if i could - why? this is the same ft232 chip with gal with logic for prosystem, there is nothing more there, but smoke and mirrors

Are you sure about this? IIRC the Atarimax SIO2PC USB interface uses a dedicated microcontroller that is able to handle the timing critical stuff all by itself. I can't tell for sure, as I don't own such an interface and the pictures on the Atarimax site don't show the chip in detail (at least I wasn't able to read the markings on the chip). The possiblity to upload new firmware into the USB interface also indicates that it's not likely to be a ft232 chip.

 

so long,

 

Hias

[atariksi]

If you're using Motor Control to ACK each byte, then I'd imagine that could also become the means to do phase-lock.

 

So long as you can guarantee the smoothness of transmission, then I don't see any problem maintaining whatever maximum speed Pokey and SIO happen to be capable of.

 

Data is expected to change on one transition and is sampled on the next transition, so you should be well and truly within a "safe" part of the waveform.

 

The SIO samples the data bit on the trailing edge of the bi-directional clock line (1->0) so the phase is defined (locked in) by the clock transition.

[HiassofT]

If you're using Motor Control to ACK each byte, then I'd imagine that could also become the means to do phase-lock.

I'm not sure if this will work reliably. The 6520A datasheet only specifies maximum delays of 0.5µS for the output signals (PAx, PBx, CAx, CBx). This means the phase of the output signal relative to PHI2 could be anything between 0 and (approx.)320°...

 

so long,

 

Hias

[atariksi]

Nyquist always applies.

 

It doesn't apply for synchronous transmissions.

 

There are plenty devices that transfer a their exact clock frequency. Consider one edge-triggered flip-flop on each end, both clocked by the same clock signal. I'm sure you agree that a matched pair of flip-flops can trasmit and receive at 1 bit per cycle, don't you?

 

Of course, for implementing this, the flip-flop on the receiver must be actually clocked by the serial clock. You might also need to do phase shifting, or send at one edge and receive on the other in the worst case.

 

There is still a question if Pokey uses the serial clock as the actual flip-flop clock or not (and I claim it does not). But if it does, then certainly you wouldn't need a 2x clock to sample rate.

 

In my rate of 333kps, I actually just went full speed on a 1mbs lpt port but I did 3 OUT DX,AL instructions to simulate clock/data signals for Atari so end up with transfer of 333kps. This in no way implies an upper limit on what Atari POKEY can handle; just ran out of bandwidth on LPT port. Need to get a faster version of LPT port and perhaps improve the algorithm.

[candle]

hias: quite sure of it - there are pictures on atarimax page of assembled devices, and i didn't see anything there indicating its using dedicated mcu for time critical job - all i see is ft232b chip with configuration eeprom

you may say it is on the bottom side, but if this is machine assembly, it would require fixture for supporting components at one side while machine places them on the other and this adds costs

http://www.atarimax.com/sio2pc/documentati...ks/IMG_6840.jpg

[HiassofT]

hias: quite sure of it - there are pictures on atarimax page of assembled devices, and i didn't see anything there indicating its using dedicated mcu for time critical job - all i see is ft232b chip with configuration eeprom

I'm still not 100% convinced. The firmware file on the Atarimax site is some 60k (bytes) in size and contains ~16k of code. OTOH the ft232 only supports 128-512 byte eeproms.

 

you may say it is on the bottom side, but if this is machine assembly, it would require fixture for supporting components at one side while machine places them on the other and this adds costs

I was more thinking about one of the microcontrollers with integrated USB (Atmel, Microchip, ...). Even FTDI has it's "Vinculum". We'd have to do a parametric search (pincount, packaging) to narrow it a little bit more.

 

But one thing is 100% sure: I really don't know what kind of chip it is :-)

 

so long,

 

Hias

[JR>]

hias: quite sure of it - there are pictures on atarimax page of assembled devices, and i didn't see anything there indicating its using dedicated mcu for time critical job - all i see is ft232b chip with configuration eeprom

you may say it is on the bottom side, but if this is machine assembly, it would require fixture for supporting components at one side while machine places them on the other and this adds costs

http://www.atarimax.com/sio2pc/documentati...ks/IMG_6840.jpg

 

I guess you didn't look very hard.

 

http://www.atarimax.com/sio2pc/documentation/usbintro.html

[candle]

JR!

guess again

ft232 runs at 48mhz, has internal ram, and its configuration is in external eeprom

i'm laughting my head off when i read technical specification done by sales people

[ijor]

I didn't read anything about 3Mhz or > 1.79Mhz in your sentence

 

There weren't any values in my original sentence. I thought they would not be needed and I assumed it was obvious what I meant. I added the values now, to make it even more clear.

 

Since I already have done 333kbs perfectly using external clock, without removing any capacitors, or any other hardware mods, I knew you were wrong.

 

I never said you can't do 333 Kbs, and you didn't mention that value before. You claimed that Pokey should be able to handle full throttle (1.79 MHz or very close) and I was replying to that.

 

Need to get a faster version of LPT port and perhaps improve the algorithm.

 

Yes, most built-in parallel ports are pretty slow. Usually PCI add-in boards are much faster. But even with PCI you might face latency issues, which depend on the motherboard, PCI bridge(s) and even other PCI installed boards.

Edited February 14, 2009 by ijor

[ijor]

but that's a side note to the pokey thing. there's no phase locked clock involved here, so you can't do 1 bit per cycle, and even if there were, there's still internal delays (as you noted).

 

I'm not sure what exactly you mean by a phase locked clock. If you mean a PLL, then of course that is not needed (why you would need a PLL when you are using the clock signal directly as clock?).

 

If what you mean is that Pokey serial logic is not actually clocked by the serial clock, then this is precisely one of the points we are debating here. Some people here claim (or at least claimed) that the bi-dir clock signal is directly used for clocking the flip-flops.

 

I wasn't talking about delays, and delay is not (exactly) the problem related to phase shifting. The problem is clock and data skew. Not in every case you need phase shifting, and once again, if you need it it's very easy to implement. Either way, this doesn't change the main point in anyway whatsoever.

[ijor]

...for me it isn't the max speed important, but anything that will allow transferring faster and more reliably than at this time...

 

candle,

 

You seem to wear two or more hats, and switch between them rather quickly. And I'm saying this friendly, because I honestly get the feeling you are a nice guy.

 

Sometimes you wear the "modest" and even "shy" guy hat: "I don't know so much about Atari", "I'm not so expert in 6502", I'm not sure, may be, perhaps, etc. Other times you wear the expert hat with very sharp replies, sometimes rather harsh, and even a bit rude.

 

In the same way, you have the "not-so-ambitious" guy hat: "I'm only trying to implement faster transfers, I'm only interested to explore Pokey synchronous mode deeper".

 

Well, nobody here said anything at all against the guy wearing this hat. And nobody here argued, even remotely, with him.

 

But then you have the "over-ambitious" hat, which gives precise figures, values and goals. And if somebody argues with this last guy, disregarding who is right and who is wrong, then he doesn't seem to like it. To the point that when I was disputing atariksi's claim that Pokey should be able to do 1.79 transfers, you agreed with him that I was using chewbacca line of defense. Pretty strange to understand that attitude when you actually agree with me that Pokey can't do "full throttle" transfers.

 

guess again

ft232 runs at 48mhz, has internal ram, and its configuration is in external eeprom

i'm laughting my head off when i read technical specification done by sales people

 

You decided to use the wrong hat here. The guy wearing the "modest" hat would have added something like "I'm not sure", "perhaps". And it would certainly be more appropiate here.

 

Atarimax is not a company as you seem to believe, it doesn't have "sales people". Atarimax is Steven Tucker, one of the most respected (may be even, the most respected of all) A8 people. He said several times that the interface has a MCU. And trust me, if he said that, you can count on his words!

[atariksi]

I didn't read anything about 3Mhz or > 1.79Mhz in your sentence

 

There weren't any values in my original sentence. I thought they would not be needed and I assumed it was obvious what I meant. I added the values now, to make it even more clear.

...

You were distinguishing between serial clock and phi clock so obviously serial clock was less than 1.79Mhz. You are not making it more clear now-- you are distorting what you stated before. Better to be honest like you claim you are.

 

>>Since I already have done 333kbs perfectly using external clock, without removing any capacitors, or any other hardware mods, I knew you were wrong.

 

>I never said you can't do 333 Kbs, and you didn't mention that value before. You claimed that Pokey should be able to handle full throttle (1.79 MHz or very close) and I was replying to that.

 

I don't have to mention 333kbs as I was arguing shift register can do full throttle: here's my quote which you also quoted back in reply in post #50:

 

I haven't read anything about POKEY requiring more than one cycle to pass data through shift register. It should handle the full throttle 1.79Mhz through its shift register. It should be able to save the bit and shift the contents. The delays would be caused by processing the bytes that come in.

 

>>Need to get a faster version of LPT port and perhaps improve the algorithm.

 

>Yes, most built-in parallel ports are pretty slow. Usually PCI add-in boards are much faster. But even with PCI you might face latency issues, which depend on the motherboard, PCI bridge(s) and even other PCI installed boards.

 

I did the 333kps test on PCI parallel port. Most PCI parallel ports go up to 1mbps.

[atariksi]

...right and who is wrong, then he doesn't seem to like it. To the point that when I was disputing atariksi's claim that Pokey should be able to do 1.79 transfers, you agreed with him that I was using chewbacca line of defense. Pretty strange to understand that attitude when you actually agree with me that Pokey can't do "full throttle" transfers.

...

Don't sling mud at the fact that you used chewbacca defense and you are covering that up now by claiming it had only to do with 1.79Mhz full throttle transfers. You said a few more things that were incorrect and that's why I stated it is "more like chewbacca defense". You stated that a full throttle like is like NO clock, "You could use a crsytal that is out by 10% of the nominal frequency, and/or with a lot of jitter, and cycle accurate software would still work.",

and other stuff including "the Pokey shift registers can't shift not even in two cycles, let alone in a single cycle."

 

You are using straw-man arguments to shove your previous chewbacca defense under the rug.

[+poobah]

I'm not sure what exactly you mean by a phase locked clock. If you mean a PLL, then of course that is not needed (why you would need a PLL when you are using the clock signal directly as clock?).

 

If what you mean is that Pokey serial logic is not actually clocked by the serial clock, then this is precisely one of the points we are debating here. Some people here claim (or at least claimed) that the bi-dir clock signal is directly used for clocking the flip-flops.

 

I wasn't talking about delays, and delay is not (exactly) the problem related to phase shifting. The problem is clock and data skew. Not in every case you need phase shifting, and once again, if you need it it's very easy to implement. Either way, this doesn't change the main point in anyway whatsoever.

i don't know exactly what they mean either ("phase locked clock" is a quote from the other posters).

it's part of their nyquist-denier non-logic.

[candle]

ijor: i belive in what i can see or in what can be shown/prooven, i'm atheistic person far from beliving in dogmats.

i've stated at verry beggining of this thread that i'm only intrested in faster than current transfer ratios using usb ft232r based converters i gave 87kbytes/s as possible speed, hias said he and his friend was doing 60-80kbytes/s already, and it would be possible to go up to 100kbytes/s but atari would not have thime for anything else - again this was done

now let me consider your behaviour: you said you know nmos asic design - good, you say something is possible, where something is not - sure, you say there is world of diffrence between going 1mbit compared to phi2/2 (approx 13% diffrence and it makes whole world! quite small world you have there)

and you keep arguing with atariksi about something you don't do, when he is doing something

so please - stop talking about way of things, start acting

i'm really hoping to see some practical results - eg another communication program that would benefit from clocked mode to do its transfers, and was able to load atr files or/and executables to atari at something more than super-hiper SIOx3 mode

and i don't know much about atari

i know what i should about hardware design, and i'm using my knowledge for building various atari extension

there are people that are far more experienced than i am, but hell - i'm still learning, and making new things

i won't stop if someone tell me something is impossible

the point is you're arguing about things you haven't check, because you have your certainity

i wonder what would atari engeeners say seeing tip/hip modes gtia modes where they've designed the chip to allow only 16 shades of one color, or 16 colors of the same shade

meanwhile, io-board i've presented some time ago is being prototyped, and production should start shortly after that

 

i must confes something though - i did pin by pin check of what is on picture i've posted with pinout of ft232b - and it doesn't match, so my strong belive in ft232 based sio2pc usb version atarimax sales is not true

still - there is a way of making sio work fast with ft232r chip

[ijor]

You were distinguishing between serial clock and phi clock so obviously serial clock was less than 1.79Mhz. You are not making it more clear now-- you are distorting what you stated before. Better to be honest like you claim you are.

 

What's wrong with you man? Do you think that if somebody disagree with you, then that give you right to call him dishonest? Or because you misunderstand my point, then you think you can know better than me what I meant, and claim I am distorting what i said, and I am being dishonest?

 

I have no problems whatsoever to admit when i was wrong. Now let's see exactly what I said:

 

Nowhere in the specs it is mentioned the max rate of the serial clock. And I think you are completely misunderstanding the issue. The issue is not the absolute frequency, the issue is the relation between Pokey main clock and the serial one. If you would overclock Pokey, and assuming it would work reliably, then you could increase the serial clock as well.

 

For starters, I was saying quite clearly that the specs don't mention anything about the max serial rate. Even then, you still understood I was claiming you were violating the specs. How I could claim you were violating the specs when I am saying there are no specs?

 

In second place, I think the third sentece explains exactly what was my point, which is the relation between the main (PHI2) clock and the serial (bi-dir) clock. So all what I was saying, is that if you would overclock Pokey (at PHI2), then you could conceivable increase the serial bi-dir clock.

 

I suggest that before acussing me of being dishonest, then perhaps, at the very least, you should ask others how they interpret my post.

 

You stated that a full throttle like is like NO clock

 

I did, and I still think that the above statement is true. And Rybags understood exactly what I meant.

 

..."the Pokey shift registers can't shift not even in two cycles, let alone in a single cycle

 

I might have been wrong about Pokey shifter needing 3 cycles per bit. If you care to check the whole thread, then you would see that more than once I added (if I'm not mistaken) when making that claim. I'm still not convinced 100% I was wrong about that. I will make some checks next week, and rest sure that if I am wrong about that, then I"ll say it explicitely without any problems.

 

I still think however, that Pokey needs at the very least 2 cycles per bit.

 

..."You could use a crsytal that is out by 10% of the nominal frequency, and/or with a lot of jitter, and cycle accurate software would still work.",...

 

atariksi, for most people (including me), cycle accurate means exactly that, just cycle accurate. So yes, cycle accuracy has no relation whatsoever with the crystal accuracy, precision or jitter. Because we are talking on one side about cycles, and on the other side about absolute time. If by "cycle accurate" software you meant something else (such as something related to absolute time), then you can't blame me of being dishonest in my reply-

Edited February 14, 2009 by ijor

[atariksi]

I'm not sure what exactly you mean by a phase locked clock. If you mean a PLL, then of course that is not needed (why you would need a PLL when you are using the clock signal directly as clock?).

 

If what you mean is that Pokey serial logic is not actually clocked by the serial clock, then this is precisely one of the points we are debating here. Some people here claim (or at least claimed) that the bi-dir clock signal is directly used for clocking the flip-flops.

 

I wasn't talking about delays, and delay is not (exactly) the problem related to phase shifting. The problem is clock and data skew. Not in every case you need phase shifting, and once again, if you need it it's very easy to implement. Either way, this doesn't change the main point in anyway whatsoever.

i don't know exactly what they mean either ("phase locked clock" is a quote from the other posters).

it's part of their nyquist-denier non-logic.

 

I never used that term "phase locked clock" either and you replied to someone who agrees that Nyquist does not always apply like you claim.

 

And to further elaborate on your previous comment:

>"knowing" the phase of the incoming signal involves obtaining information from the signal (those are samples).

 

That is not necessarily true either. I have one set up where the incoming signal start bit is connected to the ACK line of LPT port and it triggers off an IRQ on the PC end. That allows you to sync up exactly to the incoming signal and no need to sample at 2X or 3X. Another option would be if both PCs had some internal clock that was perfectly in sync to let's say to the billionths of second (to real world time) then using modulo arithmetic and arbitrarily defining some value of that modulo for both PCs to sync to, you can do perfect communications using 1X sampling. Of course, it helps to do higher sampling rates to avoid errors caused by sender/receiver not being able to do things exactly on time.

[atariksi]

You were distinguishing between serial clock and phi clock so obviously serial clock was less than 1.79Mhz. You are not making it more clear now-- you are distorting what you stated before. Better to be honest like you claim you are.

 

What's wrong with you man? Do you think that if somebody disagree with you, then that give you right to call him dishonest? Or because you misunderstand my point, then you think you can know better than me what I meant, and claim I am distorting what i said, and I am being dishonest?

 

I have no problems whatsoever to admit when i was wrong. Now let's see exactly what I said:

...

 

Nothing wrong with me man. That's not what I stated that if you disagree with me you are dishonest. And it's not about admitting your wrong either. I know what you stated and it isn't just what you quoted.

 

>For starters, I was saying quite clearly that the specs don't mention anything about the max serial rate. Even then, you still understood I was claiming you were violating the specs. How I could claim you were violating the specs when I am saying there are no specs?

 

That's one of the points. You can't say I am violating the specs if you don't know the specs.

 

>In second place, I think the third sentece explains exactly what was my point, which is the relation between the main (PHI2) clock and the serial (bi-dir) clock. So all what I was saying, is that if you would overclock Pokey (at PHI2), then you could conceivable increase the serial bi-dir clock.

 

Okay, so are admitting then PHI2 is limiting serial bi-dir rate.

 

>I suggest that before acussing me of being dishonest, then perhaps, at the very least, you should ask others how they interpret my post.

 

Wrong. If something is logically true or proven to be true by experiment, you don't need other people's opinion.

 

>>You stated that a full throttle like is like NO clock

 

>I did, and I still think that the above statement is true. And Rybags understood exactly what I meant.

 

Now you are telling me you read Rybags mind.

 

>>"the Pokey shift registers can't shift not even in two cycles, let alone in a single cycle

 

>I might have been wrong about Pokey shifter needing 3 cycles per bit. If you care to check the whole thread, then you would see that more than once I added (if I'm not mistaken) when making that claim. I'm still not convinced 100% I was wrong about that. I will make some checks next week, and rest sure that if I am wrong about that, then I"ll say it explicitely without any problems.

 

>I still think however, that Pokey needs at the very least 2 cycles per bit.

 

Okay but in the version 1.0 of your post I quoted you stated it without "if I'm not mistaken".

 

>>"You could use a crsytal that is out by 10% of the nominal frequency, and/or with a lot of jitter, and cycle accurate software would still work.",...

 

>atariksi, for most people (including me), cycle accurate means exactly that, just cycle accurate. So yes, cycle accuracy has no relation whatsoever with the crystal accuracy, precision or jitter. Because we are talking on one side about cycles, and on the other side about absolute time. If by "cycle accurate" software you meant something else (such as something related to absolute time), then you can't blame me of being dishonest in my reply-

 

Okay let's not involve t=1/f but even staying in frequency domain 10% is a lot to shove under the rug without getting labeled for chewbacca defense or other fallacy. Heck, some companies will call it a new upgraded machine if they got crystals 10% faster.

[atariksi]

Nyquist always applies.

 

It doesn't apply for synchronous transmissions.

 

There are plenty devices that transfer a their exact clock frequency. ..

 

Given just your above statements, it follows logically that full throttle clock is not the same as NO clock at all.