AND and NAND gates

[Justin Payne]

Hey all,

 

I'm trying to finish added the 32K internal mod to my Timex Sinclair 1000. The instructions are a little confusing but I think I got more of it. Still, there is one thing I think requires someone with a bit more knowledge than myself.

In the instructions here (http://www.zx81.de/english/32k-rame.htm) it states...
 

• build a simple circuit with only two NAND-gates from a 74LS00. The function is as follows:
  • When the ULA is forced to output the display-file, this is indicated to the ULA with /M1 = LOW and A15 = HIGH. Because the display-file is located in the 16-32K area, A15 for the RAM must be LOW when /M1 = LOW. The two NAND-gates form an AND.

 

My first question is...

1. If you need an AND, why not just use an AND gate, which seems to be a 7408 instead of an NAND gate (7408)?

2. Also, does that top box (with the yellow arrow) look like the wire diagram I created below it?

[alex_79]

51 minutes ago, Justin Payne said:

1. If you need an AND, why not just use an AND gate, which seems to be a 7408 instead of an NAND gate (7408)?

I'm no expert, but I guess this is simply because NAND gates are more useful and people are more likely to have those on hand rather than AND gates.

You can obtain any logic function by combining NAND gates.
You can only obtain AND functions by combining AND gates.

 

EDIT: there are cases where the propagation delay, that is the time the signal takes to pass through the gates is important and a specific sequence of gates is required, but the instruction would have stated that explicitly in that case.

 

Quote

2. Also, does that top box (with the yellow arrow) look like the wire diagram I created below it?

Yes.

 

Tie the inputs of unused gates to a fixed logic level (e.g. Vcc or ground). Leaving them unconnected (floating) makes them easily pick-up electrical noise which might affect the functionality of the entire circuit.

 

Edited April 4, 2022 by alex_79

[+Stephen Moss]

With regard to question 1...

I am not sure why they use a NAND instead of an AND, possibilities are....

1. Maybe they just had one lying around as so used that instead.
2.  Maybe they are generally easier to get hold.
3.  Maybe just because it uses more of the device.

 

With regard to question 2...

Yes, your wiring diagram looks correct, but remember with logic IC's you should never leave the inputs of unused gates floating. You can do that how you want but the simplest way is probably to connect 12, 13 & 14 together tying 13 & 14 input high, then connect 9, 10 , & 11 together tying inputs 9& 10 low.

[Justin Payne]

11 minutes ago, alex_79 said:

 

 

Tie the inputs of unused gates to a fixed logic level (e.g. Vcc or ground). Leaving them unconnected (floating) makes them easily pick-up electrical noise which might affect the functionality of the entire circuit.

 

?I did not know this but they will not be hooked up to anything...unless they will affect the internal circuity. 

Also, I love that they gave me options but this circuit is just to give me the ability to add 32K to a TS1000. I had to wait months to get this IC so just calling for an AND IC would have been a nice place to start. Now I got a project with extra steps. ?

[Keatah]

8 hours ago, Justin Payne said:

I did not know this but they will not be hooked up to anything...unless they will affect the internal circuity. 

They could affect the internal circuity by making noise inside the chip. So when you experience the future glitch, disassemble the system and ground the inputs.

[+5-11under]

NAND and NOR are universal. Either can make all the ANDs, ORs, and invert. It's maybe more of a historical thing nowadays, but back in the day, they were more popular and/or cheaper. I think they were often the building blocks for other logic gates (and more complicated logic chips), too.

[Justin Payne]

OK, another question cuz I'm a bit confused
Instructions: http://www.zx81.de/english/32k-rame.htm

Schematics: http://www.robotsandcomputers.com/computers/manuals/zx81_sch.jpg

 

• Build a simple circuit with only two NAND-gates from a 74LS00. The function is as follows:
  • When the ULA is forced to output the display-file, this is indicated to the ULA with /M1 = LOW and A15 = HIGH. Because the display-file is located in the 16-32K area, A15 for the RAM must be LOW when /M1 = LOW. The two NAND-gates form an AND.

That last sentence made me think I needed to put the output of the inputs of A15 and /M1, from the ULA, together and NAND them again. Then take that output and plug it into pin 1 on the RAM. That seems to be confirmed by the next bullet. 

• connect the A15' output of the circuit with pin 1 of the 32K-RAM chip

Now, they call it A15'. If it's the ANDing of both A15 and /M1, I'd expect them to label it as such. Also, what's the significances of the apostrophe after A15?

 

Of course, now it gets more cryptic.

• Connect A15 (cathode of D8), /M1 (edge-connector 22A), 0 volts and + 5 volts with 74LS00

D8 is a diode on the board but which A15 are they talking about? The one on the ULA or the one that we connected to pin 1 on the RAM.

Then they mention connecting /M1 to the edge connector. Does this mean I need to run a wire from the ULA's /M1 pin to the edge connector?

The "0 volts and + 5 volts with 74LS00", I assume, just means "supply it with +5volts and ground".

 

Anyone got any ideas about this?

[+Stephen Moss]

2 hours ago, Justin Payne said:

• Build a simple circuit with only two NAND-gates from a 74LS00. The function is as follows:
  • When the ULA is forced to output the display-file, this is indicated to the ULA with /M1 = LOW and A15 = HIGH. Because the display-file is located in the 16-32K area, A15 for the RAM must be LOW when /M1 = LOW. The two NAND-gates form an AND.

That last sentence made me think I needed to put the output of the inputs of A15 and /M1, from the ULA, together and NAND them again. Then take that output and plug it into pin 1 on the RAM. That seems to be confirmed by the next bullet. 

• connect the A15' output of the circuit with pin 1 of the 32K-RAM chip

Now, they call it A15'. If it's the ANDing of both A15 and /M1, I'd expect them to label it as such. Also, what's the significances of the apostrophe after A15?

Although I a not familiar with the system in question or what exactly the ULA is referring to, if pin 1 of the 32K RMA chip is address pin A15 then I think this has been covered by the schematic in your original post, as to me it appears to be no more than a textual description of that circuit. The first NAND gate NAND's A15 and M1, the second NAND with both it is inputs tied together become an inverter (change 0 to 1 and 1 to 0) thereby converting the output of the first NAND gate to the equivalent of an AND gate.

 

INPUTS  NAND     AND

00             1            0

01            1             0

10            1             0

11            0             1

 

I presume the 16-32K region discussed in reference to "output the display file" not referring to the 16-32K area of RAM, that is why address pin A15 of RAM must be low at that time otherwise both the RAM and the other data source would probably be trying to put data from their 16-32K address space on the address bus at the same time resulting in data corruption. (I also think M1 should really be MI as in Maskable Interrupt).

 

I have no idea of the significance of the apostrophe after A15, as you mentioned it is probably just to differentiate between the original A15 signal of the main system and that of pin A15 on the RAM chip. 

Quote

Of course, now it gets more cryptic.

• Connect A15 (cathode of D8), /M1 (edge-connector 22A), 0 volts and + 5 volts with 74LS00

D8 is a diode on the board but which A15 are they talking about? The one on the ULA or the one that we connected to pin 1 on the RAM.

Then they mention connecting /M1 to the edge connector. Does this mean I need to run a wire from the ULA's /M1 pin to the edge connector?

The "0 volts and + 5 volts with 74LS00", I assume, just means "supply it with +5volts and ground".

 

I think this is just telling you where to pick up the power M1 and A15 signals for the logic chip so...

If you look at the schematic you linked to the main system A15 is connected to the Cathode of D8, you take your A15 signal from there and connect it to one input of the first NAND gate.

Take the Maskable interrupt signal (described as /M1) from pin 22A of the edge connector, which in the schematic you linked to appears to indicate that the A connections are available on the top (component) side of the board (B connections on the bottom) and connect it to the other input of the first NAND gate. No need to run a wire between the ULA and the edge connector, the /M1 signal is already present on the edge connector. 

[Justin Payne]

@Stephen Moss Yes, I figured I got the wiring right on the 74LS00. You might have noticed the image I added above where I added my understanding of how to wire things up. I do know I need to add a wire off of Pin 28 to +5v.

I didn't think to check to see if A15 was connected to D8 but look at that.

So, does that mean that instead of running a wire from one of the in inputs on the 74LS00 to the A15 on the ULA that I could have just ran it to D8? Man, was that not clear at all to me.

It looks like I'll need to move those wires from the ULA to the 74LS00 to D8 and the edge connector as well as add the +5v and ground.

 

Thanks for yours, and everyone else's help with this. I'll try to put this image out on the web somewhere so that others who find the original instructions confusing can just look at my wiring image to hook everyone all up. 

 

Oh, and the ULA  (Uncommitted Logic Array) is a custom chip which controls most of the interfaces between the Z80 CPU and peripheral functions.

The ULA is responsible for:

• Generating the display (in conjunction with the UHF modulator)
• Tape and audio I/O
• Reading the keyboard

[Justin Payne]

OK. After all of your help I've created an updated diagram AND this is how I ran the wires. I haven't tested it so I guess we'll see what happens tomorring. In the mean time, I figured I'd put this out there for critiques. Ideally, I'll make this public and if someone has a better idea, I'd LOVE to hear it and I'll give y ou all credit. 

[Justin Payne]

Looks like I made one slight mistake on that diagram (A12 going to D2 instead of D3). That's corrected in both the image and on the board. Unfortunately, no video out. I did swap out the video circuit with one that will work with modern TVs but it's been so long since I did that I can't remember if I tested for video or not.? I guess I could put the original RAM chip back in just to make sure.
I did, however, test for power and I'm getting it everywhere so that's a good sign. I also made sure the ol' video switchbox and cable were good by using it with my XEGS.
I have an O-scope so I check to make sure I'm getting something out.

Man, I wish things would just work the first time I do them. ?

[+Stephen Moss]

On 4/8/2022 at 3:21 PM, Justin Payne said:

So, does that mean that instead of running a wire from one of the in inputs on the 74LS00 to the A15 on the ULA that I could have just ran it to D8? Man, was that not clear at all to me.

It looks like I'll need to move those wires from the ULA to the 74LS00 to D8 and the edge connector as well as add the +5v and ground.

As long as you are connecting to the right signal it should not matter where along the signal path you pick it up from, so for MI you could have taken that from pin 10 of IC1, pin 27 of IC or pin 22A of the edge connector, equally for A15 you could have picked that up from pin 18 of IC1, pin 5 of IC3 or the cathode of D8.

I can only assum that the instruction mention D8 and pin 22A as they are easier to get at.

 

In regard to the PCB conenction diagram you posted...

1. You have the 0V pin of the NAND IC labeled as "GRN", if that is what is in the data sheet then that is fine, but generally Ground is abbrievited to "GND" and the GND or 0V pins of logic IC's would be VEE for TTL logic and VSS for CMOS logic although there tends to be a lot of mix and match these days with regard to logic pins by people who should know better.
2.  You should also show connections tying the unused input of the NAND chip to power or GND rather than leaving them floating as was mentioned in a prevous post, if you leave unused inputs floating that can result in unwanted logic glitches appearing on the outputs you are using.
3. Assuming you have the orientation of the RAM IC chip, yo uhave the power and ground pin designations the wrong way round, power (VCC, TTL logic/VDD, CMOS logic) should be top right and gound (VEE, TTL logic/VSS CMOS logic) should be bottom left. Technically, if the conenctions are correct the labeling does not matter, but better to get it correct otherwsie it might confuse someone in the future.

[Justin Payne]

@Stephen Moss 

 

"I can only assume that the instruction mention D8 and pin 22A as they are easier to get at." Good to know. I didn't know if the person who created these instructions did that because it was important to get that signal further down the circuit's logic.

 

1. "You have the 0V pin of the NAND IC labeled as "GRN"". LOL! I didn't even notice that. I meant to put GRD. I'll correct that.

2. "You should also show connections tying the unused input of the NAND chip to power or GND." Has been added in my latest image.

3. "you have the power and ground pin designations the wrong way round". Wow! Again, another good catch. Fixed.

[Justin Payne]

WARNING! I made a mistake in my diagram.

Turns out what I thought was 5v was actually 9v. Whoops. I started to smell the RAM cooking so hopefully I didn't fry that. I disconnected the 32K RAM and circuit and put the original 2K RAM back in, which is what I should have done to begin with. I still have no image so now I'm trying to troubleshoot the replacement 3rd party video circuit I installed. I'm getting video signal but not 100% sure what I'm looking and so more investigation is required.