Richard Chandler Posted April 30, 2022 Share Posted April 30, 2022 This is to announce the discovery of a new, hitherto unknown, behavior of the RETI and RETN instructions. As everyone knows, the maskable interrupt can be enabled and disabled by using the EI and DI instructions respectively, which control the state of the interrupt enable flip-flops (IFF1 and IFF2). The CPU does not accept this kind of interrupt directly after an EI instruction, but only after the one following EI is executed. This is so that ISRs can return without the danger of being interrupted immediately after re-enabling interrupts if the /INT line is still active, which could cause a stack overflow. Well, recently, I discovered that, as in EI, all forms of the RETI and RETN instructions defer the acceptance of the maskable interrupt for one instruction, but this only occurs when IFF1 and IFF2 have different states prior to the execution of either of these instructions, which, obviously, can only be caused by a preceding NMI response. This can be tested on Visual Z80 Remix: https://floooh.github.io/visualz80remix/ Furthermore, unlike EI, a sequence of RETI/RETN instructions will not prevent an INT request from being accepted. It's time to update your emulators! 1 Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.