How exactly do cartridges with RAM generate a R/W signal?

[bigmessowires]

Because the CPU's R/W signal isn't exposed on the cartridge connector, cartridges with RAM need to fake it and synthesize their own /WE for the RAM. How exactly is this done? Are there schematics of working solutions? I don't think it would work to use an address bit directly as /WE since I don't think the timing of when address bits change relative to the data bits would be correct for RAM writes. I'm thinking it would need a delay circuit of some type, maybe an RC circuit controlled by an address bit. I swear I once saw a schematic of such a thing, but now my searches are coming up empty. Thank you!

[Ben_Larson]

You are right that the R/W signal is not exposed on the cartridge connector and that actually complicates things a lot on games that have extra RAM.

 

The way it's solved is that the RAM read addresses are different from the RAM write addresses.  In that way, the cartridge can determine if an access to the cartridge RAM is a read or a write.

 

It's wasteful because it means that twice as many addresses are needed.  So on a Superchip game, for example, 256 bytes at the beginning of the 4K ROM space are wasted for access to the 128 bytes of RAM.  That means there's only 4,096 - 256 = 3,840 bytes available for program data in each bank.

 

As for how they actually generate the signals, I think that's done internally on the Sara chip.  If you wanted to do your own implementation using discrete logic, you would need to implement the glue logic to generate the /WE and /OE signals when a read or write address was decoded.  I don't think the timing is necessarily as critical as you think, though.  For a write, the data just needs to be present (and held steady) within some window of time after the control signals are set.

Edited October 1, 2023 by Ben_Larson

[tschak909]

Darn, I was gonna answer this. Yeah, you have to bifurcate the address space into read and write sections.

 

-Thom

[bigmessowires]

Thanks, I do understand about splitting the address space, but I'm wondering specifically how the write enable signal for the RAM chip is generated. Is there a schematic I could look at? Maybe I'm wrong, but I don't think it could be as simple as OR-ing and AND-ing some address bits together to make a write-enable signal. The required timing for /WE relative to the address and data wouldn't be met. I'm thinking there must be some kind of delay built-in to the circuit that generates /WE for the RAM chip.

[+bent_pin]

34 minutes ago, bigmessowires said:

Thanks, I do understand about splitting the address space, but I'm wondering specifically how the write enable signal for the RAM chip is generated. Is there a schematic I could look at? Maybe I'm wrong, but I don't think it could be as simple as OR-ing and AND-ing some address bits together to make a write-enable signal. The required timing for /WE relative to the address and data wouldn't be met. I'm thinking there must be some kind of delay built-in to the circuit that generates /WE for the RAM chip.

One of the address bits (MSB) is different between the range of read and write addresses, that's the r/w pin and the rest are the address pins. This demultiplexes the addresses automatically.

 

Here is a hastily drawn example:

[Kroko]

Here is a schematic for E0 Bankswitching in discrete logic:

http://www94.pair.com/jsoper/2600_pb_bs.html

[bigmessowires]

Right, that's true from a programmer's model. But from a hardware designer's perspective I'm pretty sure that more is needed. In that diagram if you used A4 directly as /WE, then you would have the address bits changing simultaneously with the /WE signal that latches them, leading to data corruption. It would not meet the RAM chip's hold time requirement on the address bits relative to /WE.

 

For an example of what I'm talking about, look at this bank-switching cartridge design. This isn't external RAM, but it's somewhat similar.

 

The resistor and capacitor that are connected to 74LS04N in the center of the schematic are essential for making it work. They add some amount of delay to the CLK signal for the 74LS174N, so the rising edge of the clock won't happen until a short time after the address bits change, instead of simultaneous with the address bits change. Without that RC delay circuit, this design probably wouldn't work.

 

But an external RAM has a level-sensitive /WE signal, not an edge-sensitive clock input like this bank-switch circuit. I believe it needs some kind of circuit element that drives /WE low a short time after the address bits change, then after a delay, drives /WE high before the address and data change again. Basically it needs to guarantee that address and data are stable for the whole time that /WE is low.

 

If there's an old cartridge design with RAM that's been reverse-engineered, or a new cartridge design with RAM that's open source but doesn't involve a microcontroller, I could look at the schematic to see how exactly it generates the /WE signal for the RAM chip.

 

 

Edited October 1, 2023 by bigmessowires

[bigmessowires]

4 minutes ago, Kroko said:

Here is a schematic for E0 Bankswitching in discrete logic:

Great, yes this is more like what I'm thinking of. I'll look at this in more detail. Thank you!

[+5-11under]

You could probably just use @bent_pin's lovely diagram to get going. I often need delays when incorporating latches, but typically not with SRAM. Check out some timing diagrams, and writing isn't too much different than reading, so if it can read, it can usually write.

 

[+bent_pin]

3 minutes ago, 5-11under said:

You could probably just use @bent_pin's lovely diagram to get going. I often need delays when incorporating latches, but typically not with SRAM. Check out some timing diagrams, and writing isn't too much different than reading, so if it can read, it can usually write.

 

This

My diagram is extra simple. I omitted all the discrete components. It just depends on what ram chip you'd like to use.

 

Ask, if you have further questions. Lots of great users here can answer them.

[+SvOlli]

Also, I can tell you, how it works with the SARA extra 128 bytes RAM.

This chip is just put alongside of the ROM (or in my case EPROM+GAL). It has full address decoding, so it can select itself, what to do.

For the ROM side, you just put $FF in the first 256 bytes of each page, so the bus is "virtually untouched", since it's open collector and the "0"s drive the bus.

[bigmessowires]

Thanks all. I'm actually not looking to build an Atari cartridge, but just to understand how the RAM's write enable signal is generated for Atari cartridges with on-board RAM. From having looked at this a while back, I remembered that it was possible, but not the details of exactly how it's done. The ASCII schematic of E0 bankswitching has the answer, if you stare at it long enough. Basically you need to create a monostable multivibrator that's normally high but outputs a short low pulse whenever there's a rising edge on one of the address bits (or on a combination of address bits AND-ed and OR-ed as you desire). You can adjust the capacitor and resistor values to get a specific pulse length, then use this pulse as your /WE signal. This guarantees the /WE won't be asserted until a short time after the address bits have settled, and that it will be de-asserted before the address and data change again, assuming you've tuned the pulse width correctly.

 

For anyone who's curious, my actual goal is to support in-system programming of a flash ROM SIMM in a 68K Macintosh, where there is no /WE signal present at the SIMM socket. I hope to use the same technique as these Atari cartridges do to repurpose one of the address bits as /WE for the flash.