ICD MIO Replica board build completed

[BillC]

7 hours ago, Marius said:

This what you write... does this also apply to CSS's The Black Box!? 

It most certainly does, in 1992 I visited Bob in Buffalo due to BB instability issues, while enroute to visiting a friend in PEI. Bob was able to swap out some capacitors which resolved the issue, in later years I realized this was probably due to a Phi2 timing problem with the 800XL I normally used. 

[MEtalGuy66]

11 hours ago, BillC said:

It most certainly does, in 1992 I visited Bob in Buffalo due to BB instability issues, while enroute to visiting a friend in PEI. Bob was able to swap out some capacitors which resolved the issue, in later years I realized this was probably due to a Phi2 timing problem with the 800XL I normally used. 

Its a completely relative issue and every atari has it. The only question is whether in any particular group of connected hardware, the skew being caused is putting the data bus out of time with PHI2 enough to cause invalid/incorrect bus states to be interpreted/expressed by the CPU. I promise you, if you have a particular "setup" that works, if you add/remove enough hardware (capacitive/inductive load) from the databus, this realtionship will go out of range and create the problems.. Its like setting the ignition timing on an engine.. Just nowhere near as easy to "adjust"..  the 'PHI2fixer' simply modfies the phi2 timing of the device that it is connected upstream of, and ensures that it's timing is not skewed from system PHI2 timing. It does not do ANYTHING to correct the system-wide skew/delay that is caused by increasing the load on the databus.   This will be about the 1000th time ive explained this crap ad-infinitum on these forums..

 

Next, Fuck-why will chime in and spew a bunch of bullshit based on his experience with the "jay miner 800" and incognito board..  

and another cycle of dejavu, catch22 will be complete..  

Edited November 26, 2023 by MEtalGuy66

[Marius]

Well, I must say, that I do not want to go back to the tragedies of losing a Ramdisk content (and the system keeps running, and the system thinks the ramdisk is reliable, so overlay files from the BBS system were saved and loaded from that Ramdisk, which eventually made the whole BBS crash... including partitions). 

 

Or the moments where a partition was completely killed due to some odd behavior. 

 

No... I must honestly say... I do not want bring that back. So I think I will keep the good memories, and for now I will stick with slightly less problematic hardware.

 

 

[MEtalGuy66]

I am an IDE Plus 2.0 guy, myself..

 

[ijor]

On 11/26/2023 at 1:58 PM, MEtalGuy66 said:

I promise you, if you have a particular "setup" that works, if you add/remove enough hardware (capacitive/inductive load) from the databus, this realtionship will go out of range and create the problems.. Its like setting the ignition timing on an engine.. Just nowhere near as easy to "adjust"..  the 'PHI2fixer' simply modfies the phi2 timing of the device that it is connected upstream of, and ensures that it's timing is not skewed from system PHI2 timing. It does not do ANYTHING to correct the system-wide skew/delay that is caused by increasing the load on the databus.

 

I think that the main issue with modern add-ons is not so much the PHI2 timing, but its signal quality. At least this is a serious problem if you attempt to run a modern FPGA or CPLD directly from PHI2. A modern FPGA would interpret glitches on the PHI2 signal as extra clock transitions and the logic will break. I understand this is the main target with something like "O2 fixer", with the idea to improve PHI2 signal quality.

 

Hardware add-ons based on old components is a completely different story, I guess. Typically old components would be immune to these tiny glitches, the same way that the original motherboard chips are. I can see that too much additional capacitance on the buses could be a serious problem here instead.

 

If I read correctly the original MIO schematics there seems to be up to 5 TTL loads on some data bus signals !? I don't remember if Atari ever published official PBI specifications, but being unbuffered it was probably designed to drive only a single TTL load. No wonder that it was "problematic". I can see that in the MIO remake BOM you replaced a couple TTL chips with CMOS HCT parts, I guess precisely to mitigate this problem?

 

Are Black Box schematics available somewhere, original or reverse engineered?

 

[+bf2k+]

18 hours ago, MEtalGuy66 said:

I am an IDE Plus 2.0 guy, myself..

 

Me too... I have a Rev C and a Rev H.

 

Although I have had a few MIOs myself. 

[+Larry]

What are some of the common modes of failure on MIO's?  From my own experience, both of my MIO's failed during their warranty periods and had to be returned for service.  IIRC, they did repair my units and return them to me (rather than sending me replacement units).  I can't remember -- the MIO could be powered with a regular Atari 9V adapter, couldn't it?  I still have one boxed up in the garage that has the new rom. 

 

I always liked the big ramdisk, and it was nearly as fast as an internal ram expansion.  AA member @1050 helped me set up a MyDos version with a couple of small patches and autorun that would check and boot from the ramdisk.  Kinda neat! 

[_The Doctor__]

MIO failure was power supply section and two chips centered nearest the PBI connector, a failed memory chip once in a blue moon. Capacitors were sometimes retrofit to the MIO when problematic machines arose. The only choice was cheap caps, the cure would have been buffering and signal conditioning.

 

This also occurs with SIO might we add, @lotharek actually has a winner in his powered SIO hub which buffers and conditions SIO signals very nicely.

 

Atari had a buffering cable for PBI / the 1090 variants you can now see/make/buy are normally buffered at minimum. That is by design to keep the average Atari cost down, if someone wanted more they were to bear the expense. But this was not disseminated in a formal paper, they just expected people to see or find this out themselves from looking at what was done. A problem beings the 1090 did not get to the shelves, not a good chance to see the buffered cable or buffered 1090. I think the buffered PBI cable was called a Julia cable, something along those lines, this cable buffered only the signals that were determined to need buffering/conditioning. Not sure the specifications were ever set in stone, but the cables and 1090s exist.

Edited November 28, 2023 by _The Doctor__

[kenames99]

yes, afaik it was the julia "cable". I have been looking but found zero info on it. I would think it is just like the PBI buffering in the 1450XL. would not be to hard to bring that to life, at least I wouldn't think so.

 

Ken

 

[Marius]

On 11/27/2023 at 9:32 PM, MEtalGuy66 said:

I am an IDE Plus 2.0 guy, myself..

 

Me too. I am very happy with these devices. And I do not see myself change to anything else soon. But... I have some very fond nostalgia memories of the blackbox (not all positive, but some of the memories are the best) so I was wondering whether I should go back to blackbox or not...

[kenames99]

I do have an IDE Plus Rev D and like it quite a lot.

 

Ken

 

[t0ri]

Hi!

 

@130xeguy

 

I only now noticed the thread. Hat off and many thanks for recreating the device for the Atari. I know how complex and demanding this task is. I admire your perseverance

 

regards

tOri