Building & Testing the Re-imaged Atari 1450XL

[Dropcheck]

On 12/12/2023 at 8:20 AM, kheller2 said:

I wonder how close that wire wrap board is to this:

 

 

Looks to be a much more refined version.  Almost ready for release.

[Dropcheck]

FYI:  Update.  I've finished the initial entry into Diptrace, my PCB CAD program of choice, of the 1400XL schematics.  Now I'll be going through and reconciling it to the ref designations on the 1450XL bare board I have on loan from @kheller2 and the 1450XL schematics.  Some parts are known to be unattainable now, so I'll substitute for the closest match as possible.  I've already run across a couple of instances where a part was labeled with the same ref designation as another, so that will have to be sorted out too.   That process might take a bit longer as I'll have to reconcile the prototype 1450XL board and at least two different schematics along with correctly matching the actual part and source from @Vandal968 excel BOM. 

 

With Christmas racing to get here, you might not get an update for awhile.  I will pop up here as soon as I can.

[reifsnyderb]

On 12/16/2023 at 6:13 PM, Dropcheck said:

FYI:  Update.  I've finished the initial entry into Diptrace, my PCB CAD program of choice, of the 1400XL schematics.  Now I'll be going through and reconciling it to the ref designations on the 1450XL bare board I have on loan from @kheller2 and the 1450XL schematics.  Some parts are known to be unattainable now, so I'll substitute for the closest match as possible.  I've already run across a couple of instances where a part was labeled with the same ref designation as another, so that will have to be sorted out too.   That process might take a bit longer as I'll have to reconcile the prototype 1450XL board and at least two different schematics along with correctly matching the actual part and source from @Vandal968 excel BOM. 

 

With Christmas racing to get here, you might not get an update for awhile.  I will pop up here as soon as I can.

I know you are using Diptrace.  I've been using KiCad 6 and was just wondering what was added in KiCAD 7.  It turns out KiCAD 7 appears to be able to display a background image to allow a board to be reverse engineered.  This is a feature I've been looking for for a while.   🙂

 

[Dropcheck]

14 hours ago, reifsnyderb said:

I know you are using Diptrace.  I've been using KiCad 6 and was just wondering what was added in KiCAD 7.  It turns out KiCAD 7 appears to be able to display a background image to allow a board to be reverse engineered.  This is a feature I've been looking for for a while.   🙂

 

I just recently discovered that Diptrace 4.3 has that capability too.  I had thought I'd have to go with Sprint Layout or maybe Kicad.  I've tried numerous times to wade into Kicad to create some pcb, but I found the interface to be about as clunky as Eagle's.  I don't want to memorize a zillion arcane keyboard shortcuts on top of a zillion other arcane keyboard shortcuts for a zillion other Windows apps.  Not saying that Diptrace doesn't have it's quirks, but it's a familiar blanket now.  It can export and import several different other electronic CAD files with some degree of accuracy and so far does everything I need it to do. 

 

 

[+Guitarman]

This thread is a great read. When I purchase my board, I also ordered all the needed parts that were on the BOM from Mouser and Digikey. I think the only part I still don't have is one of the GAL chips. Two of the three were still available from Best, so I was able to get those. I have moved twice since that time, so the board and all the parts to build it out are still boxed in a storage garage!! I have finally, recently, started re-organizing my entire collection to get a handle on everything. I still have the plan to build out my board, so this thread is getting tagged!!

 

[Geister]

Guitarman, looking at the Reno collection, that gold disk I think came with the Eidolon game.  I don't remember if it had a purpose or it was just a decorative pack-in.

[Dropcheck]

FYI:  Update on progress.  Painstaking slow.  But it is beginning to come together for a initial faithful recreation of the 1450XL board.  Just a few more parts to add and then I'll start filling in the traces between parts and updating a schematic at the same time.

 

[Geister]

Between you and Brian, I'll be able to realize my 1984 dream of owning a 1450XLD and a 1090 expansion chassis, even if all the board must remain naked. 

 

Edited to account for my nerve damaged typing.

Edited January 9 by Geister

[Geister]

OK, half-way there.

[sup8pdct]

On 12/13/2023 at 12:20 AM, kheller2 said:

I wonder how close that wire wrap board is to this:

 

 

Looks nothing like it. Pictured board has head amplifiers, stepper control etc like a 1050. ie doesn't use a std floppy mech. It has 8040 and 2797 but cannot see a 8155. can see unused connectors for 2nd bare mech.

another schematic i have that is possibly a 1090 board,  has a 6116 ram chip. this isn't present either.

A dump of the rom from this would be good to see.

 

 

[Dropcheck]

FYI:  Update
      I've reached the point at which I am beginning to gather and verify all BOM information.  This means I am about ready to send off the first prototype of the remade 1450XL board for manufacturing.  Hopefully in about a week.  I'm somewhat confident that I don't have fatal errors in the schematics, but I fully expect to have to make minor corrections and then do a second, hopefully final production run.  
      
      I believe I will go with a two layer pcb with slightly higher board thickness for the first prototype run.  It is routing with no real issues already.  I've found no definite indications of installed parts that don't have traces on either the top or bottom of the original board that I have to compare with. So I begin to doubt that Atari actually did a four layer board at least for the prototype board I have in hand.  It appears they just chose to do a thicker board. This is not a small board, measuring about 352mm x 242.5mm.  That alone drives the cost up.  If I did four layer, I'd have to change board manufactures due to JLCPCB not being able to do blind/buried vias.  That would drive even more cost. Right now at two layers at this board size, the total cost for 5 boards is a little over $100 including shipping from China.  Not pocket change!
      
      I've gone through and corrected silkscreen errors and mismatched parts references, using Vandal968's BOM and checking against the Atari labeled 1400XL and 1450XL as well as Sobola' schematics.  In the intervening years since Vandal968's assembly thread began, some parts are no longer available from either Mouser or Digikey, my main part sources.  Ebay is somewhat suspect and even Jameco is on their last inventory for some parts.  Best Electronics is limiting the number of parts you can order in one order, and he also is probably getting close to selling out on some things.  Even then some parts may have to be scavenged from either an 800XL/1200XL.  What I could substitute I did.  I have left some parts on the board that were not populated by Vandal968 in his working unit for historical purposes.  They will be marked as such on the BOM and schematics I release.  This first board will try to be as faithful a reproduction as possible while eliminating confusing errors that serve no good purpose. 

 

     Once I have this version of the 1450XL nailed down, I'll move onto improvements and removal of useless features for the next version.  A big part of that will be to see if a parallel disk drive can be added and functional.  

[+Stephen]

Awesome!

[+mytek]

4 hours ago, Dropcheck said:

I've found no definite indications of installed parts that don't have traces on either the top or bottom of the original board that I have to compare with. So I begin to doubt that Atari actually did a four layer board at least for the prototype board I have in hand.

That's very interesting and counteracts the info originally coming from Curt. Keep in mind that traces are usually not done in the middle layers if it can be avoided, since these are normally reserved for power planes (Ground and +5V). So all the interconnections other than power will occur on the top and bottom layers, with the power buses being done through internal connections to the middle layer power planes via the pad through holes where required.

 

EDIT: albeit my memory of what he said could be flawed.

 

4 hours ago, Dropcheck said:

If I did four layer, I'd have to change board manufactures due to JLCPCB not being able to do blind/buried vias.

Blind/buried vias are not required if only using the middle layers for power planes. I've done several 4-layer board designs via JLCPCB without the need for these (e.g., 1088XEL, 1088XLD, 576NUC+). When uploaded to JLCPCB the designs are treated like normal 4-layer boards - nothing special.

[+kheller2]

@Dropcheck Have you looked at the official TONG schematics to see if they did the modem differently, and maybe used more readily available components overall?  I've also wondered what  the Parallel Disk Controller schematics from April 84 were to be used for/on.  I would love to think it was a 1090 card.  But... probably not.

[Dropcheck]

Quote

That's very interesting and counteracts the info originally coming from Curt. Keep in mind that traces are usually not done in the middle layers if it can be avoided, since these are normally reserved for power planes (Ground and +5V). So all the interconnections other than power will occur on the top and bottom layers, with the power buses being done through internal connections to the middle layer power planes via the pad through holes where required.

   I do remember Curt saying such too and that's why I was surprised as well when I saw so many GND and power traces on both sides of the board I have on hand.  It is worth it to note that the board is using GND, +5V, as well as +12V and -5V for some of the components.  Could the GND traces I'm seeing on the board be used to separate the other voltage lines in some way?  This is the most complex board I've ever tried to reproduce.  So assuming that one middle layer is GND.  The other middle layer is +5V.  That would leave power traces for -5V and +12V on either top or bottom layers. 

 

Quote

Blind/buried vias are not required if only using the middle layers for power planes. I've done several 4-layer board designs via JLCPCB without the need for these (e.g., 1088XEL, 1088XLD, 576NUC+). When uploaded to JLCPCB the designs are treated like normal 4-layer boards - nothing special.

    That is good to know.  Obviously my understanding on what constitutes blind/buried vias is wrong.   

[AtariGeezer]

4 hours ago, kheller2 said:

@Dropcheck I've also wondered what  the Parallel Disk Controller schematics from April 84 were to be used for/on.  I would love to think it was a 1090 card.  But... probably not.

I have compared these to my back engineered schematic of the wire wrap design of the Parallel Disk Controller and found some of the missing circuits.

[+mytek]

4 hours ago, Dropcheck said:

Could the GND traces I'm seeing on the board be used to separate the other voltage lines in some way?

Maybe.

 

I think the best way to establish what's going on with the power is to pick a TTL gate with a known pin connection scheme such as a 74LS08 which has +5V on pin 14 and GND on pin 7. If you look at those pins and don't see any top or bottom trace going to it that would suggest it gets its power from a middle layer that can't be seen. You could do the same for any chip known to require -5V and +12V as well.

[Dropcheck]

11 hours ago, mytek said:

Maybe.

 

I think the best way to establish what's going on with the power is to pick a TTL gate with a known pin connection scheme such as a 74LS08 which has +5V on pin 14 and GND on pin 7. If you look at those pins and don't see any top or bottom trace going to it that would suggest it gets its power from a middle layer that can't be seen. You could do the same for any chip known to require -5V and +12V as well.

It appears that on the TTL  and the custom chips the only +5V trace is usually going from the power pin to the bypass caps and then stops.  On the -5V and +12V power there are traces coming from power in to the various pins across the length of the board, sometimes on top, sometimes on bottom as the case maybe.  That would seem to confirm a middle +5V layer and infer a GND middle layer as well.  So a 4 layer board it appears to be afterall. 

 

Now it should be a simple matter to configure Diptrace for the two inner layers and trying routing.  I'm not looking forward to the JLCPCB cost quote.  😔

[Dropcheck]

So far based on what I'm seeing in trying to route a 4 layer board in Diptrace is that it will route if I designate both inner layers as generic signal layers, ie just an additional two layers like the top/bottom for any traces to run.  As soon as I try to reserve one or the other of the inner signal layers specifically for GND or +5V, I get thrown into buried/blind via country.   I've sent a message on Diptrace's forum to see if I'm missing something in Diptrace or if it's a feature.

 

I don't know if the original board is routed with a specific signal per layer or it's generic as well.  I suspect it is not generic.

[+mytek]

3 hours ago, Dropcheck said:

It appears that on the TTL  and the custom chips the only +5V trace is usually going from the power pin to the bypass caps and then stops.  On the -5V and +12V power there are traces coming from power in to the various pins across the length of the board, sometimes on top, sometimes on bottom as the case maybe.  That would seem to confirm a middle +5V layer and infer a GND middle layer as well.  So a 4 layer board it appears to be afterall. 

Good to hear that what I recalled Curt saying turned out to be correct, so at least some of my memory cells apparently remain intact 👍

 

4-layer really is a better way to go insuring solid clean power distribution, and a lot of added possibilities for trace routing on the top and bottom layers. Having two full copper layers sandwiched also creates a very large high frequency capacitor to better decouple any noise issues coming from the logic switching of the individual chips.

 

12 minutes ago, Dropcheck said:

So far based on what I'm seeing in trying to route a 4 layer board in Diptrace is that it will route if I designate both inner layers as generic signal layers, ie just an additional two layers like the top/bottom for any traces to run.  As soon as I try to reserve one or the other of the inner signal layers specifically for GND or +5V, I get thrown into buried/blind via country.

I'm not familiar with Diptrace, but I do find it odd that you need to go through hoops to create a 4-layer power planed board within it. As an example, I use a very old layout program from ExpressPCB that has always been given away for free in order to tie you to their PCB fabrication service. In that layout program all I need to do is go to board properties and check the 4-layer box. Then using the link to schematic feature I can click on either a ground or +5V connection and all the same pads will become highlighted in blue. Next I simple hover over a highlighted pad, left click and select whether that pad will get assigned to a power inner layer (+5V) or a ground inner layer and then select either thermal or solid connection to that layer. Granted I had to purchase separately a program to allow me to export gerbers so that I wouldn't be held hostage to the ExpressPCB fabrication service, and I also don't have fancy 3D views or auto-routing, but because of its ease of use and absolute reliability it works for me. Speaking of reliability, both my brother I tried KiCad a few years back, with me in Linux and my brother in Windows, and we both experienced multiple crashes while testing it for a few days. This doomed it for us, since it simply wasn't acceptable to have our work lost that easily. Hopefully by now things are much more solid with it.

 

26 minutes ago, Dropcheck said:

I've sent a message on Diptrace's forum to see if I'm missing something in Diptrace or if it's a feature.

I hope you get some clarification on how this is done within that program.

 

[Teapot]

1 hour ago, Dropcheck said:

So far based on what I'm seeing in trying to route a 4 layer board in Diptrace is that it will route if I designate both inner layers as generic signal layers, ie just an additional two layers like the top/bottom for any traces to run.  As soon as I try to reserve one or the other of the inner signal layers specifically for GND or +5V, I get thrown into buried/blind via country.   I've sent a message on Diptrace's forum to see if I'm missing something in Diptrace or if it's a feature.

 

I don't know if the original board is routed with a specific signal per layer or it's generic as well.  I suspect it is not generic.

I also use DipTrace and JLCPCB and have made dozens of boards without a problem.

 

But only one 4-layer board. And I hand route everything - I find it fun and an interesting challenge to make it look nice as well.

 

I just opened that 4-layer board in 3.3.1.3 and only selected "Unroute All" and then "Run Autorouter" and it worked as expected. Updated the copper pours of the middle layers and it then passed the DRC. Still only the default via style in the list.

 

I don't have any suggestion for a solution, just verification that DipTrace will do the job.

[Dropcheck]

2 hours ago, Teapot said:

I also use DipTrace and JLCPCB and have made dozens of boards without a problem.

 

But only one 4-layer board. And I hand route everything - I find it fun and an interesting challenge to make it look nice as well.

 

I just opened that 4-layer board in 3.3.1.3 and only selected "Unroute All" and then "Run Autorouter" and it worked as expected. Updated the copper pours of the middle layers and it then passed the DRC. Still only the default via style in the list.

 

I don't have any suggestion for a solution, just verification that DipTrace will do the job.

I'm using Diptrace 4.3x.  Hope that is not an issue. 

 

So you created Inner Layer 1 and 2.  What type of layer did you use signal or plane?

[Teapot]

1 hour ago, Dropcheck said:

I'm using Diptrace 4.3x.  Hope that is not an issue. 

 

I wouldn't think so. I'm using the old version until I finish a big project of many boards.  Only two more to layout...

 

1 hour ago, Dropcheck said:

So you created Inner Layer 1 and 2.  What type of layer did you use signal or plane?

They're both planes. Inner 1 is Gnd and Inner 2 is Vcc. Each has a single snap to border copper pour.

 

I tried an experiment where I added a pair of blind via styles (one to each inner layer from the top) and reran the autoroute. It used them even when there was no conflict with going all the way through. The autorouter doesn't appear to add new styles. Maybe you have some extra styles defined that you can remove.

[Dropcheck]

1 hour ago, Teapot said:

I wouldn't think so. I'm using the old version until I finish a big project of many boards.  Only two more to layout...

 

They're both planes. Inner 1 is Gnd and Inner 2 is Vcc. Each has a single snap to border copper pour.

 

I tried an experiment where I added a pair of blind via styles (one to each inner layer from the top) and reran the autoroute. It used them even when there was no conflict with going all the way through. The autorouter doesn't appear to add new styles. Maybe you have some extra styles defined that you can remove.

Let's take this out of the forum.  It's getting off topic.  IM sent.  Hopefully we can figure out what I'm doing wrong with Diptrace.  I've not had this much trouble with it before.

[Dropcheck]

Well thanks to @Teapot, I think I am back on track now.  Diptrace and I were fighting each other for a time, but now with his help the waters have calmed and we are in harmony again.  @Mytek caught me in an bad assumption that the board was not a four layer board, and probably saved a failed board manufacture attempt. 

 

So what can go wrong now?  (I didn't actually say that did I?  Dumb....🤕)

 

The BOM is done, I have managed to complete a test route of the board as 4 layer.  Now comes the prettify part, where I add nice touches and fully annotate the board and make it as close to the original board as possible, but better.   I'm still hoping for a submission to JCLPCB on Sunday for the prototype, but we'll have to see.

 

I've been collecting chips, connectors and various and as-sundry parts over the last couple of months.  I hope to make a final parts order to Mouser/Digikey Monday.  Then it's a waiting game for the boards to arrive from JCLPCB.