Atari 800 XL Remake

[reifsnyderb]

Parts are ordered for the 600XLM board.  Parts for this board, with shipping, are about $145 from Mouser.  This does not include the Atari VLSI chips, Teensy, and SIO port, of course.  The memory, CPU, and connectors really run up the bill.  I estimate an 800XLM will cost around $20 more in parts.  Adding a Teensy is another $25 plus shipping.

 

Edit to add:  Some connectors still need added....such as the 3 needed for the U1MB.

Edited December 10, 2021 by reifsnyderb

[reifsnyderb]

One change was made the the 800XLM board.  That was to add a connection from the internal cartridge CPLD to the MMU.  

 

The problem I was contemplating was how to enable access to flash the internal cartridge memory without the internal cartridge firmware "running" at the same time.  The design of the Atari is such that if both the left and right cartridges are installed at the same time only the left cartridge will be executed.  However, the XL just has one cartridge slot and it's the "left" cartridge.  So, I think I can take advantage of this and the process will go like this:

 

The internal cartridge CPLD is connected to a jumper.  If this jumper is installed, the internal cartridge memory can be written to.  If there is no jumper, the internal cartridge is in "run" mode and can only be read from.

 

So, when the jumper is missing, the internal cartridge memory will be mapped by the MMU to the left cartridge slot.  When the jumper is added, and the cartridge is in "write" mode the internal cartridge will be mapped by the MMU to the right cartridge slot.  As the XL has internal BASIC mapped to the left cartridge slot, the internal BASIC will run.  The internal cartridge memory will be accessible via the 8k "window" just below BASIC at $8000-$9FFF and can be controlled via CCTL at $D500-$D5FF.  So a rather simple BASIC program will be able to flash the internal cartridge by setting the proper cartridge bank in CCTL, reading from a file, and writing to the cartridge location.  

[_The Doctor__]

if people are allowed to suggest modern stuff then you don't have to do that either... but it seems only one side of the coin need be looked at... this is why people end up making add on boards and such other mods to stuff later on to add back in what they thought would be useless later on... like Cartridge ports or SIO ports or even special stuff custom made to overcome the issues so folks can have lets say a fujinet, or other Cartridge based devices and new homebrews that are only on cart at this time, etc etc. I am always for adding functionality, fun, and simplification, but sometimes that comes to the detriment of a project... I want to see your project succeed and be used by many... not just obtained to get it done and sitting in a pile of stuff people get to support a project but ultimately don't like or use.

 

I don't think drams are necessary but it could be an option for some. I personally have drawers full of em and they're dirt cheap. It doesn't take much to support both, and provided a spot a header and add on pcb could allow it if a person wanted to go that route as well... possibilities are endless...

 

As an afterthought I went back and skimmed along the thread. I didn't see anyone say you had to do a thing or must do a thing, I believe everyone is being helpful. Save people indicating what you are or are not allowed to say, suggest or do.

[reifsnyderb]

15 minutes ago, _The Doctor__ said:

if people are allowed to suggest modern stuff then you don't have to do that either... but it seems only one side of the coin need be looked at... this is why people end up making add on boards and such other mods to stuff later on to add back in what they thought would be useless later on... like Cartridge ports or SIO ports or even special stuff custom made to overcome the issues so folks can have lets say a fujinet, or other Cartridge based devices and new homebrews that are only on cart at this time, etc etc. I am always for adding functionality, fun, and simplification, but sometimes that comes to the detriment of a project... I want to see your project succeed and be used by many... not just obtained to get it done and sitting in a pile of stuff people get to support a project but ultimately don't like or use.

 

I don't think drams are necessary but it could be an option for some. I personally have drawers full of em and they're dirt cheap. It doesn't take mach to support both, and provided a spot a header and add on pcb could allow it if a person wanted to go that route as well... possibilities are endless...

 

As an afterthought I went back and skimmed along the thread. I didn't see anyone say you had to do a thing or must do a thing, I believe everyone is being helpful. Save people indicating what you are or are not allowed to say, suggest or do.

After you brought this up, I was thinking earlier that there could be the possibility of an add-on board capability, like you mention, so that somebody could add back in CAS and RAS support to the parallel bus.  All that would be needed would be an area set aside with some through-holes in the main board.  This add-on board could be made using some header pins, a CPLD, a programmable delay line, and other support components.

 

I'll investigate the idea in the near future and before the next phase of boards get ordered.  This add-on CAS/RAS compatibility board would have to be developed, of course.  Maybe it could straddle the BASIC ROM and OS ROM....or something like that.

Edited December 10, 2021 by reifsnyderb

[reifsnyderb]

Two sets of headers will be added to both the 600 XLM and 800XLM for anyone who has the uncontrollable urge to make a small daughter board to re-add CAS and RAS back to the board for the parallel port.....

 

This can be done with a CPLD, programmable delay line, and some auxiliary components such as a JTAG connector, capacitors, etc.  Probably cost about $15 in parts....

[Mathy]

Hello @reifsnyderb

 

Robert/Redhawk has developed a Delay line replacement not that long ago.  Check out this thread.  Not that much bigger than two jumpers.

 

Sincerely

 

Mathy

 

[reifsnyderb]

1 hour ago, Mathy said:

Hello @reifsnyderb

 

Robert/Redhawk has developed a Delay line replacement not that long ago.  Check out this thread.  Not that much bigger than two jumpers.

 

Sincerely

 

Mathy

 

Thanks!

[reifsnyderb]

Ok.  I've added J945 and J946 so that a custom board could be developed and plugged in if someone wants to re-add CAS and RAS on the 600 XLM.  Both are 30mm apart and offset to provide better support for any board.  C49 was moved to allow for clearance.  I'll see if the same is possible for the 800XLM soon.

 

[reifsnyderb]

1 hour ago, Mathy said:

Hello @reifsnyderb

 

Robert/Redhawk has developed a Delay line replacement not that long ago.  Check out this thread.  Not that much bigger than two jumpers.

 

Sincerely

 

Mathy

 

I was just looking at the files.  I may get some of them made the next time I order boards.

[reifsnyderb]

Ok.  The compatibility connectors (JP945 and JP946) have been added for the 800XLM as well.  The board has to be different than the 600XLM due to being in a different location.  Also, there is no interference with J1600 as J1600 has shorter pins.

 

Either way, CAS and RAS could now be added back to the parallel bus for both the 600XLM and 800XLM boards if so desired.

 

Edited December 11, 2021 by reifsnyderb

[BillC]

5 hours ago, reifsnyderb said:

I was just looking at the files.  I may get some of them made the next time I order boards.

Vintage Computer Center sells this device, they reduced the size by using an SMD IC.

https://www.vintagecomputercenter.com/product/atari-co60472-delay-line-replacement

Edited December 11, 2021 by BillC

[+mytek]

8 hours ago, BillC said:

Vintage Computer Center sells this device, they reduced the size by using an SMD IC.

https://www.vintagecomputercenter.com/product/atari-co60472-delay-line-replacement

And it's very reasonably priced

[reifsnyderb]

Boards for the 600XLM are finished and shipping within the day.  On another note I think I figured out how to increase the 800XLM to 2MB of SRAM.

Edited December 14, 2021 by reifsnyderb

[Crc_Error]

Whats the difference between the 600xlm and 800xlm? Whats the website to buy boards from?

[reifsnyderb]

34 minutes ago, Crc_Error said:

Whats the difference between the 600xlm and 800xlm? Whats the website to buy boards from?

There's no place to buy them at this time and they are being beta tested.

 

Both the 600xlm and 800xlm are designed to be almost 100% drop-in replacements for the 600xl and 800xl boards.  Presently, they are the same with the following differences:

 

600xlm:

 

1 MB SRAM, Teensy 3.5 to handle internal SD card based solid state hard disk.  80 column capability is planned and should be possible by updating the firmware on the Teensy.  The Teensy 3.5 will also have a real-time clock and could be programmed to act as a USB device.

 

800xlm

 

1 MB SRAM (2 MB SRAM may be possible but banking will have to be custom)

Teensy 4.1 to handle internal SD card based solid state hard disk.  80 column capability is planned and should be possible by updating the firmware on the Teensy.  The Teensy 4.1 will also have a real-time clock.  The Teensy 4.1 could also be programmed to act as both a USB host and USB device.

512k internal cartridge memory with cartridge control circuitry.

 

Both use the original Atari VLSI chips (i.e. ANTIC, GTIA, etc.) but use mostly surface-mount components for everything else.  Many standard upgrades already have headers and sockets in place.  i.e.  Adding the Ultimate U1MB board requires just plugging it in and swapping a jumper.

 

 

The banking concept for a 2MB 800xlm would be for bit 6 of PORTB to enable a special banking mode whereby all other bits of PORTB are used for banking.  (Set bit 6 to 0 for the special banking mode.)  Under normal operation, with bit 6 set to 1, all other bits of PORTB would work as per 130XE specifications.  So, to access all 2MB, set bit 6 to 0 then use all the remaining bits to select the 16k bank.  If you want to disable the BASIC chip, you would have to set bit 6 to 1, set bit 1 to 1, then could go back to 2MB access by setting bit 6 back to 0.  The operations of bits 0,1,& 7 in "normal mode" would be latched in place while in 2MB banking mode.  Keep in mind this is a concept.  The MMU and EMMU are both programmable so there are some things to be worked out.   ?

 

The first beta boards allowed me to fix about 6 or so small problems.  I believe all the problems are worked out in the boards that are coming but will find out soon.   ?

 

The ultimate goal is to have a serious contradiction of a "modern" 8 bit Atari computer.  ?

 

 

 

 

 

 

Edited December 14, 2021 by reifsnyderb

[Crc_Error]

Great stuff.  All involved in this project deserve an award!  Looking forward to purchasing either a 600 or 800 version in the future.  

[reifsnyderb]

2MB of SRAM in the lower left corner of the 800XLM board.  The EMMU has control over both CE# and CE2 chip select lines for the memory.  So by criss-crossing the CE# and CE2 lines between the SRAM banks, one 1MB SRAM bank will be selected at a time.  (Or neither selected.)  The EMMU has the clock signal coming in so it can also pulse the appropriate CE2 line.  (At least that's the theory.   ?   )  The EMMU chip has also been swapped out for the smaller ATF1504 due to both size and availability.  Also, since the JTAG has been figured out, there is no need to be concerned about removing the chip.  I'll open source the CPLD, Teensy firmware, and JTAG programming info when released.

 

On another note, I spent 8 hours typing in the ALPA assembler into my 800XL only to find out that Atari BASIC must have some sort of memory allocation bug as because after some debugging I discovered that 1000 bytes of the text buffer string was taking up over 6000 bytes of memory.  In short I was running out of memory on just the DIM lines.  This problem doesn't exist in the Altirra emulator with Altirra BASIC.  So, I've got some EEPROM chips ordered and a burner so as to burn Altirra BASIC into the BASIC ROM as it seems ideal for the task....and it's open source.   ?

   

 

 

[BillC]

8 hours ago, reifsnyderb said:

Boards for the 600XLM are finished and shipping within the day.  On another note I think I figured out how to increase the 800XLM to 2MB of SRAM.

IIRC the Newell memory upgrades were released to public domain when the deal with FTe fell through, I have an 800XL with a Newell 1MB upgrade.  I remember having the schematics of the 1MB version at one point which showed an extra logic connection to allow 4MB. There were 1MB versions for several different Atari models, and there was also a 1-4  megabyte version for the 800XL/1200XL.

Manuals for these upgrades available at: https://archive.org/search.php?query=atari newell

 

I also found some Newell RAM upgrade schematics, but didn't check them to verify whether they were capable of 4MB.

http://ftp.pigwa.net/stuff/collections/atari_forever/Extension/Newell memory upgrades/

While the folder linked above is on pigwa the schematics themselves appear to be missing, but I did find the following which does show the 4MB connection:

http://ftp.pigwa.net/stuff/collections/atari_forever/Extension/Memory Upgrade/Atari XL 8-bit Memory Upgrade Page.htm

 

While these legacy upgrades were based on DIP DRAM it should be possible to convert them to work with SRAM. While the Newell 1MB upgrade does have ANTIC mode, it loses control of internal BASIC(I installed a separate toggle switch).

 

Edited December 14, 2021 by BillC

[reifsnyderb]

5 hours ago, BillC said:

IIRC the Newell memory upgrades were released to public domain when the deal with FTe fell through, I have an 800XL with a Newell 1MB upgrade.  I remember having the schematics of the 1MB version at one point which showed an extra logic connection to allow 4MB. There were 1MB versions for several different Atari models, and there was also a 1-4  megabyte version for the 800XL/1200XL.

Manuals for these upgrades available at: https://archive.org/search.php?query=atari newell

 

I also found some Newell RAM upgrade schematics, but didn't check them to verify whether they were capable of 4MB.

http://ftp.pigwa.net/stuff/collections/atari_forever/Extension/Newell memory upgrades/

While the folder linked above is on pigwa the schematics themselves appear to be missing, but I did find the following which does show the 4MB connection:

--snip--

 

5 hours ago, BillC said:

http://ftp.pigwa.net/stuff/collections/atari_forever/Extension/Memory Upgrade/Atari XL 8-bit Memory Upgrade Page.htm

 

While these legacy upgrades were based on DIP DRAM it should be possible to convert them to work with SRAM. While the Newell 1MB upgrade does have ANTIC mode, it loses control of internal BASIC(I installed a separate toggle switch).

 

 

If I were to use bit 6 for banking as well, 4MB would be possible but there would be no control over BASIC and OS ROM.  I am trying for the best of both worlds.

 

 

[Mathy]

Hello reifsnyderb

 

Will the real time clock be RT8 compatible?  (while I'm on my wishlist: I'd prefer a RT8 compatible clock that get's it's time from an atomic clock.  There seem to be three different ones in the world (depending on the region you are in), but I've heard that there is a chip that will handle them all.)

 

The Newell updates lose a couple of features when they go big.  IIRC, the 4MB version is in banked memory all the time.

Bit 6 BTW controles Missile Command on the XEGS.  Why not freeze the signals for BASIC, OS ROM/RAM, (Missile Command) and Selftest when either bit 4 or bit 5 or both go low?  That way you get 1MB with full software controle over these four signals.  You could use a second address in the $D3xx range to access 2, 4, 8 or 16MB.

 

Sincerely

 

Mathy

 

 

[reifsnyderb]

1 hour ago, Mathy said:

Hello reifsnyderb

 

Will the real time clock be RT8 compatible?  (while I'm on my wishlist: I'd prefer a RT8 compatible clock that get's it's time from an atomic clock.  There seem to be three different ones in the world (depending on the region you are in), but I've heard that there is a chip that will handle them all.)

 

The Newell updates lose a couple of features when they go big.  IIRC, the 4MB version is in banked memory all the time.

Bit 6 BTW controles Missile Command on the XEGS.  Why not freeze the signals for BASIC, OS ROM/RAM, (Missile Command) and Selftest when either bit 4 or bit 5 or both go low?  That way you get 1MB with full software controle over these four signals.  You could use a second address in the $D3xx range to access 2, 4, 8 or 16MB.

 

Sincerely

 

Mathy

 

 

I was just going to have it update off of the Teensy clock.  However, do you know what chip to use for atomic clocks?

 

I am not using the Newell updates.  The plan was to be XE compatible unless bit 6 is low.  (Since we won't have Missile Command.  lol)  Then, when bit 6 is low, BASIC and OS ROM would be latched in place so those bits could be used for banking.  (Bit 5 would also be used for banking when bit 6 is low, as well.)  Though, since you mentioned it, latching BASIC and the OS ROM when bit 4 is low would work too.  However, there would be no opportunity for ANTIC banking.  I'll give the scheme some more thought but will, as always, welcome any ideas in this matter.  As long as the correct circuitry is in place, the banking schemes can be re-programmed at any time via the CPLD's.

 

Best Regards,

 

Brian

 

 

 

[reifsnyderb]

I forgot to add that the goal is for the real time clock to be RT8 compatible.

 

[reifsnyderb]

Boards came in.  Just "little" bit of soldering and hopefully I'll have a "new" 600XLM!

 

 

[kenames99]

2 minutes ago, reifsnyderb said:

Boards came in.  Just "little" bit of soldering and hopefully I'll have a "new" 600XLM!

 

 

hey, feel free to send me one!

 

Ken

 

[kenames99]

hi,

  I know I promised right after the weekend but had a bit of trouble finding the 1450xl but here are the schematics for 1400XL and 1450XL machines. interesting stuff in these.

 

Ken

 

1400XL-schems.zip 1450XL Schematics.zip