Atari 800 XL Remake

[+mytek]

I have yet to see a 3D printed case of that size that actually looks good. Although I guess there are professional high quality 3D printers that will produce something a bit closer to an injection molded part, but it probably wouldn't be cheap.

 

[ClausB]

On 11/30/2021 at 5:59 PM, reifsnyderb said:

I took about an hour to determine if there would be a problem as the Teensy 3.5 is 5 volt "tolerant".  This means it's good for 5 volt inputs on the digital pins only but has only 3.3 volt outputs.  As I doubted the Atari chips would be ok with 3.3 volt outputs if +5vdc was needed I was concerned and thought I'd still need level shifters until I realized the SIO is "active" low.  So it should be just fine.   

 

MOS 6502 and 6520 data sheets say VIH is 2.4V min. And so is VOH. I presume POKEY is similar. The T3.5 outputs a solid 3.3V, so even active high circuits are fine with it. I've used T3.2 and T3.5 in several retrocomputing projects without level shifters successfully.

Edited December 4, 2021 by ClausB

[reifsnyderb]

1 hour ago, bfollowell said:

 

I don't think there were designed to be put into a new case, not that you couldn't if you designed one and had it printed. I'm pretty sure these were meant as replacements for original motherboards inside existing cases.

 

Yeah, these boards are meant as drop-in replacements for the originals.

[+bf2k+]

11 hours ago, reifsnyderb said:

Yeah, these boards are meant as drop-in replacements for the originals.

Well they certainly do look nice and this is one of the most interesting threads I've seen here in a while... thanks for sharing.

[reifsnyderb]

The 600xlm now has the potential for an 80 column display via SIO due to the addition of U1501, R1500, R1501, and R1502.

 

On the 800xlm pathfinder board I am still waiting on memory and a couple other components.  FedEx said they'd deliver them yesterday, then today, now it's re-scheduled again.  I hope they aren't lost.  Incidentally, I placed two orders with Digikey on Wednesday.  The one via USPS arrived Saturday and the other, more important order, is the FedEx shipment.  Go figure.

 

I was able to verify the GTIA chip and ANTIC chip I am using for the 800XLM are both good by swapping chips with one of my 800's.  

 

Also, programing those CPLD's with the JTAG connections is no longer a mystery.  To make a long miserable story short this was eventually accomplished on a Linux laptop with a FT232H breakout board, a breadboard, and OpenOCD.  I knew it could be done as I found blog files but most of the documentation is written as though you already know how to do it.  Also, do not try to do this on a Windows 10 machine as the device drivers are a major problem.  I think Windows 10 is swapping your selected device driver with it's own every time you try a change but didn't feel like dedicating another day to figuring it out.  (I am pretty sure there is a way to stop Windows from doing this...)  So, I put Linux on an old laptop and got it done.  While I am using the FT232H breakout board on a breadboard, the schematic for the JTAG "adapter" is attached and I'll get some boards made the next time I order boards.

 

The 800XLM is basically on hold until FedEx gets the memory in my hands.  Hopefully, it will be fully functional by the end of this week.

 

I'll get the program for the CPLD done that I've decided to call the Memory Control Unit (MCU) as it replaces U26, U27, U28, and U29 on a standard 800XL.  Of course, using SRAM helps drop the chip count, too.  The initial program will be simple and will omit banking until I get the bugs out and get it working.  Once it works, adding banking will be quite easy.

 

I also checked and have a PHI2 signal but no HALT from ANTIC.  However, I know ANTIC is good and am just assuming that since there isn't any memory ANTIC isn't going to be very happy yet.

 

 

[+mytek]

1 hour ago, reifsnyderb said:

The 600xlm now has the potential for an 80 column display via SIO due to the addition of U1501, R1500, R1501, and R1502.

Care to explain how that is to be accomplished? Will SIO be sending the character information to your Teensy which will be creating the 80 column video?

 

1 hour ago, reifsnyderb said:

I'll get the program for the CPLD done that I've decided to call the Memory Control Unit (MCU) as it replaces U26, U27, U28, and U29 on a standard 800XL.

Unfortunately the lines have been blurred on the meaning of the abbreviation MCU. Because that is also a common term that refers to Micro-Controller-Unit usually used to describe a single chip computer, or in other words a microprocessor, RAM, ROM, and I/O all on one substrate. So for instance the Teensy and the PIC could rightfully be called MCU's (LINK).

 

Personally I've always liked the term MMU instead which stands for Memory-Management-Unit. Just a case of "tuh may to" - “tuh mah to"

 

1 hour ago, reifsnyderb said:

On the 800xlm pathfinder board I am still waiting on memory and a couple other components.  FedEx said they'd deliver them yesterday, then today, now it's re-scheduled again.  I hope they aren't lost.  Incidentally, I placed two orders with Digikey on Wednesday.  The one via USPS arrived Saturday and the other, more important order, is the FedEx shipment.  Go figure.

Wow any time I order from Digi-key lately, as in this past year, I can expect to wait between 1-1/2 to 2 weeks no matter how I've specified the shipping to be. Usually I find that shipping isn't the real bottleneck, and instead it's the wheels inside Digi-Key that are slow to turn.

 

Edited December 6, 2021 by mytek

[reifsnyderb]

56 minutes ago, mytek said:

Care to explain how that is to be accomplished? Will SIO be sending the character information to your Teensy which will be creating the 80 column video?

 

Unfortunately the lines have been blurred on the meaning of the abbreviation MCU. Because that is also a common term that refers to Micro-Controller-Unit usually used to describe a single chip computer, or in other words a microprocessor, RAM, ROM, and I/O all on one substrate. So for instance the Teensy and the PIC could rightfully be called MCU's (LINK).

 

Personally I've always liked the term MMU instead which stands for Memory-Management-Unit. Just a case of "tuh may to" - “tuh mah to"

 

Wow any time I order from Digi-key lately, as in this past year, I can expect to wait between 1-1/2 to 2 weeks no matter how I've specified the shipping to be. Usually I find that shipping isn't the real bottleneck, and instead it's the wheels inside Digi-Key that are slow to turn.

 

The theory is that 80 column character info could be sent through SIO to the Teensy.  I read somewhere that it was done before.  (I think somebody wrote a V: driver.)  Admittedly, I don't know what compatibility problems would be presented by doing it this way.  On the 600XLM board, running those 4 joystick lines from the lower right side of the board to the upper left is rather problematic as 3 of the 4 board layers are heavily used.  The 4th layer, the ground layer, could possibly be used if need be.  But I'd rather just keep it to ground.  If there is no other way to ensure compatibility then I'll re-visit running those 4 joystick lines.  Let me know what you think.

 

Maybe MCU isn't the best choice of terms.  ?  But since MMU was already taken I figured it made sense.  Quite frankly, I wonder why the MMU is called the MMU when it really just enables or disables chips depending upon the address.  But, if anyone has a better name for a chip that handles the SRAM access and banking I'll take it.  I guess this memory access control CPLD is more like Freddie on an XE....

 

 

 

EDIT:  I just looked at the board and realized there may be an easy way to run those 4 joystick lines anyhow.  I was only considering running the lines up the right and over the top.  However, the Teensy 3.5 location makes it possible to run the 4 joystick lines across the bottom of the board and intercept the Teensy 3.5 about 1/3 of the way up the board to the left.  Those Teensy connections are digital, as well.  I'll take another look at it in the morning.

 

 

 

 

Edited December 6, 2021 by reifsnyderb

[+mytek]

When I asked about the use of SIO I was simply curious of what you had in mind, not that it's a bad idea. in fact since a driver needs to be loaded anyway to use the 80 column video, having an SIO version instead could make things even better, since the driver could be automatically loaded like what several SIO peripherals already do. However it does mean that programs that were designed specifically for the XEP80 will need to be patched, such as AtariWriter 80. Good thing is, there really weren't that many applications written with the XEP80 in mind, so not a lot of patching required either

 

The MMUs that got used in the XL/XE line were nothing more then a way to compress the required glue logic associated with memory address decoding into a single package via a PLD. Essentially the function is still considered memory management, and in the case of the XL and XE, is directly involved in selecting or deselecting the RAM, Basic ROM, and the first stage of decoding for the general I/O hardware. Sure seems like memory management if you ask me

 

If there is more than one MMU, then you can do what was done in the 576NUC+, and give one of them an additional prefix as in EMMU which was responsible for decoding the extended RAM banks in that system.

 

[reifsnyderb]

Sounds like a plan.  To be consistent I'll call the other CPLD an EMMU.

 

On the 600XLM, the joystick lines are now extended over to the Teensy 3.5 as well.  Only one resistor needed moved and some +5v lines re-routed.  The lines are nice and straight, too, and not the zig-zag mess I thought would have to be employed.

 

The SIO idea can still be employed, of course.  But with the joystick lines 80 columns will be easier.

[reifsnyderb]

I still had a white screen.  While troubleshooting I figured the problem was either the EMMU or something else.  So, I started poking around the processor with my scope.  After a lot of searching I discovered the problem.  The pin numbers from the W65C02S 40 pin PDIP are different from the W65C02S 44 Pin PLCC.  In most cases it's just off by one.  I never caught it.  Hacking this board to handle this would require somehow mounting the processor on the breadboard and tying it into the board.  It would be ugly.  

 

While I was hoping to get this board running in whatever hacked form I could get it running, I think the right solution is to update the next generation of boards with the changes and get them coming.  

[+mytek]

1 hour ago, reifsnyderb said:

The pin numbers from the W65C02S 40 pin PDIP are different from the W65C02S 44 Pin PLCC.

This exact same thing bit my butt about 20 years ago when I was designing a color video overlay board with a PIC chip. The initial breadboard was with a DIP version, and in the PCB layout I switched to a PLCC to reduce the footprint. I got the sample boards and assembled one of them only to discover my mistake. Back then PCB manufacture in even a small sample quantity was extremely expensive and I was on a shoestring budget. I got so discouraged that I never again pursued the project and let it die. Thankfully that has all changed with the advent of boards made in China

 

But yes it still sucks, so i feel for you.

 

[reifsnyderb]

I was going to get them made at Oshpark.....then found out they wanted around $1,200 for 3.  I really wish there was a place in the US that would make boards for not much more than what China does.

 

I am thinking that I'll get the 600XLM boards made next.  They should be a little cheaper and I do have a dead 600XL to try one in.

[reifsnyderb]

My belief is that I didn't blow the 65C02 processor but I'll order another just in case.  I was also impressed that the memory chip is designed such that if it's accidentally installed backwards there shouldn't be any damage.  

[+mytek]

1 hour ago, reifsnyderb said:

My belief is that I didn't blow the 65C02 processor but I'll order another just in case.  I was also impressed that the memory chip is designed such that if it's accidentally installed backwards there shouldn't be any damage.  

I believe many of the Atari chips must be the same way. Or if nothing else they are pretty tough because I've accidentally inserted many of them backwards without realizing the mistake for quite some time after power has been applied, and they survive without any ill affect.

 

[reifsnyderb]

I went over the processor and it's accompanying circuitry.  It turned out there was another problem so that's fixed.  The 600XLM board has been ordered.

 

Also, I was thinking about having many components placed by machine then found out many components had extra costs or required a minimum of 3000 pieces.  So, I decided to add the component values silkscreened to the board.  That way it will be much, much faster to solder on all those components.

 

The JTAG board has been ordered as well.   ?

 

 

In the future I'll have to change out the CPLD's to a more available version, too, as the 5vdc ATF1502's are getting scarce.  But that won't be a big problem once this is working.

 

 

[reifsnyderb]

Ok.  Unless there are any more suggestions.  (Which are very much welcome!)  I think I added the last feature to the 800XLM board for now.  (If I re-configure the Teensy arrangement, in the upper left corner, I can make even more space.)  While I have a couple minor details to work out yet, added is an experimental internal cartridge capability.  Those components are numbered in the 16xx range.  Basically, the idea is that flash ROM at 1601 can be programmed with a cartridge and the CPLD at 1600 can provide for the cartridge interface and banking to access it.  The flash ROM has access to 8 data bits and 13 address bits.  The CPLD (at 1600) has access to 8 data bits and 8 address bits so as to act as the cartridge control.  The MMU has a chip select line running to the cartridge control CPLD at 1600.  So, when the MMU is setup correctly, if a cartridge is inserted this internal cartridge would be disabled.  If a cartridge is absent, the internal cartridge would be enabled.  In theory, this will allow for SpartaDOS X to be programmed onto the flash rom at 1601.  When the jumper at JP1600 is installed, the computer will be able to write to the flash memory and a simple BASIC program could do this.

 

The Jumper JP 954 (to the right of the video section) will disable this feature.  This jumper is actually connected to the MMU but has to be out of the way to allow clearance if an Ultimate 1MB is installed.

[kenames99]

hey, yea I totally agree with that! only reason I put them on the 1066 ram board for the 1090xl remake is to reproduce the original board in it's original form. I did that and it works so that design is an antique and I will not produce any more. I have other plans for memory upgrades and other add ons for the 1090xl. Also, since you are real good at hardware, feel free to design up any thing you wish for it. it is on github and open to everyone. I have a minor adjustment to make on the 50 pin card edge to be 100% but everything else is ready AFAICT. any observations or corrections needed are welcome. thanks.

 

Ken

 

 

On 11/23/2021 at 5:37 AM, tf_hh said:

PLEASE - Don´t use these old crap DRAMs expansions any more! For years these ones have always been the biggest source of trouble. Every real experienced Atari hardware guy will commit this. Countless hours have been spend to make such spaghetti monsters work fine. And, together with modern CPLD and/or FPGA based, external expansions there are new problems.

 

It´s a great point of evolution that today all memory expansions uses SRAM. So my 2 cents:

 

- Include the standard 512 KB expansion in your logic

- Include the possibitily to add an U1MB board

 

Switching between these options is possible using a few jumpers. You have more than enough free space on the new PCB ?

 

 

[reifsnyderb]

4 minutes ago, kenames99 said:

hey, yea I totally agree with that! only reason I put them on the 1066 ram board for the 1090xl remake is to reproduce the original board in it's original form. I did that and it works so that design is an antique and I will not produce any more. I have other plans for memory upgrades and other add ons for the 1090xl. Also, since you are real good at hardware, feel free to design up any thing you wish for it. it is on github and open to everyone. I have a minor adjustment to make on the 50 pin card edge to be 100% but everything else is ready AFAICT. any observations or corrections needed are welcome. thanks.

 

Ken

 

 

 

Are you using pins 41 (CAS) & 44 (RAS) on the parallel port?  I am asking because this remake uses SRAM and both pins are now NC as there is no reason nor capability for CAS and RAS.

[kenames99]

On 11/21/2021 at 9:09 PM, reifsnyderb said:

I could probably put buffering into the 800 XLM but there isn't space for the 600 XLM.  

 

I am thinking a 74LS245 would work as a buffer?  Would there be a difference between DMA and 1090xl?  It would be preferable to do both.   ?

hi,

  the 1400xl only has real buffering on the data lines thru a 74ls245. that is driven by a pld output, that one would tell the 'ls245 when to be active. I have not taken the pal apart or tried to find it's logic. the r/w line is also directly connected, that would direct whether it is writing to pbi or reading from pbi. the address lines and control lines are directly connected to PBI so they are good to go. hope that helps. if you need or want 1400xl and/or 1450xl schematics just let me know. I will likely post them here after weekend is over, I have to find the 1450 one. thanks.

 

Ken

 

[kenames99]

19 minutes ago, reifsnyderb said:

Are you using pins 41 (CAS) & 44 (RAS) on the parallel port?  I am asking because this remake uses SRAM and both pins are now NC as there is no reason nor capability for CAS and RAS.

I am not, even the 1066 memory board generates it's own /ras and /cas signals. iirc it uses the B02 clock signal.

 

Ken

 

[reifsnyderb]

5 minutes ago, kenames99 said:

hi,

  the 1400xl only has real buffering on the data lines thru a 74ls245. that is driven by a pld output, that one would tell the 'ls245 when to be active. I have not taken the pal apart or tried to find it's logic. the r/w line is also directly connected, that would direct whether it is writing to pbi or reading from pbi. the address lines and control lines are directly connected to PBI so they are good to go. hope that helps. if you need or want 1400xl and/or 1450xl schematics just let me know. I will likely post them here after weekend is over, I have to find the 1450 one. thanks.

 

Ken

 

Thanks for checking.  I wouldn't mind taking a look at the 1400xl and 1450xl schematics.  But no rush.

[reifsnyderb]

3 minutes ago, kenames99 said:

I am not, even the 1066 memory board generates it's own /ras and /cas signals. iirc it uses the B02 clock signal.

 

Ken

 

Good to hear.  I was worried that this could be a compatibility problem.

[_The Doctor__]

is it possible any of the external memory cards and similar external extensions use ras and cas, or the myriad of other pbi devices? The are quite a number of items that use the pbi or cart devices, eprom programmers you name it, memory, hard drives, floppy, MULTI I/O devices, what of future devices. What harm is there in supplying whats already on the machines and keeping a standard... unless you have some special case new signals that can't be added to the pinout... but then you could have a jumper or switch swap them.

Edited December 10, 2021 by _The Doctor__

[reifsnyderb]

46 minutes ago, _The Doctor__ said:

is it possible any of the external memory cards and similar external extensions use ras and cas, or the myriad of other pbi devices? The are quite a number of items that use the pbi or cart devices, eprom programmers you name it, memory, hard drives, floppy, MULTI I/O devices, what of future devices. What harm is there in supplying whats already on the machines and keeping a standard... unless you have some special case new signals that can't be added to the pinout... but then you could have a jumper or switch swap them.

My preference would be not to omit those signals if at all practical, however, 3 chips would have to be added in order to supply them and none of those chips are needed with sram or anything else.  Also, the chip for the schmidt trigger was connected as well.  (This chip is now only being used for the reset button.)  One of the chips is the delay line and I am not sure of it's availability.  I suppose some sort of modern replacement could be found for the delay line (maybe even something programmable?) but it didn't make sense to track something down that wasn't used and has a low probability of being used.

 

Not having extra lines ran to the schmidt trigger chip (U19) means it can be re-located.

 

Edit to add:  I did a quick search and found there are programmable delay lines.  The cas and ras could probably be added with a programmable delay line and a CPLD.  This would add about another $7 to the cost of components on the board.

Edited December 10, 2021 by reifsnyderb

[+mytek]

I think it's time to move on from using DRAMs. Your board is not a clone, and should not be held to the same old standard as far as memory is concerned. If people want exactly what was done in the past, then they can either A) stick to the stock XL motherboard, or B) buy one of the clone boards that got produced a while back. Your board like many of my projects is forward looking, and will offer so much more that makes sense in this day and age. I really love what you've been doing in your redesign ?

 

Edit: Besides... this is your project, and if others want something else the door is wide open

 

Edited December 10, 2021 by mytek