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New Intellivision console coming?


Rev

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Elektronite probably wants something that can play Elektronite games.  That's something Mister can't do, unless someone makes a cartridge interface for it.  Mister is open source but I'm not sure about the different system cores.  An Intellivision system also needs Intellivision controllers, and there's now a solution for that.

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A cartridge interface for Mister can be implemented with a bit of electronic design, same for the controller ports in order to use oroginal controllers (but there are modern controllers under distribution here on the forum).

Probably investing on existing open source solutions already in place would be wiser than reinventing the wheel 

 

Edited by artrag
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4 hours ago, artrag said:

A cartridge interface for Mister can be implemented with a bit of electronic design, same for the controller ports in order to use oroginal controllers (but there are modern controllers under distribution here on the forum).

Probably investing on existing open source solutions already in place would be wiser than reinventing the wheel 

 

Mister can use Intellivision controllers through usb adapters.  A more direct controller connection would be better.  If Mister is open source someone can base a new device from it, just as Mister was based on the work from the Mist project.

 

51 minutes ago, Jaxivision said:

Does FPGA stand for something?

Field programmable gate arrays can emulate processors and electronics hardware better than software emulation.

Edited by mr_me
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34 minutes ago, mr_me said:

Mister can use Intellivision controllers through usb adapters.  A more direct controller connection would be better.  If Mister is open source someone can base a new device from it, just as Mister was based on the work from the Mist project.

 

Field programmable gate arrays can emulate processors and electronics hardware better than software emulation.

 

 

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Back at the Classic Gaming Expo in Las Vegas in 2014, I proposed to Keith Robinson, an HDMI board that would drop into the flashback case, run cartridges and use the flashback controller. He sat there rolling his eyes during the entirety of my pitch. Obviously, it never went anywhere. 

 

Fast forward to 2022. Elektronite is associated with a company that is looking to bring out an FPGA based classic Intellivision console. Think Collectorvision Phoenix, but for the Intellivision. This console is NOT intended to be a 40 dollar 'flashback' unit. It will be a premium console. It is not aiming at the budget flashback market. The console will be fully licensed and legal. We have access to an FPGA chipset developed in Europe. There is a real possibility of the console having built in Intellivision games. This is not 'pie in the sky' but a serious attempt at bringing this console to market. 

 

Everything here is subject to change. As many people realize, this is not a trivial project. First of all, the console in my opinion should have:

 

- HDMI output

- Be able to run all Intellivision cartridges including JLP, LTO Flash! and other new 'homebrew' cartridges

- Support the Intellivoice

- Support the ECS

- Able to use standard Sears/Intv II controllers

- Able to use @Games Intellivision flashback controllers

- Ability to load games using an SD card 

 

Of course, having a console such as this being made, it would be a shame not to allow people to create 'super' Intellivision games based on a similar architecture. We would like to support something similar to the Intellivision 3. 

 

We proposed a similar thing back in 2014. This was the 2014 proposed spec that would have been supported in the FPGA. The console, of course, is intended to be fully backward compatible with original Master Component software. Everything below is subject to change. It is simply a proposal and suggestions are welcome. 

 

Proposal for Enhanced INTV hardware specification
---------------------------------------------------------
Intended implementation as a FPGA ASIC or as a an enhanced emulator
-------------------------------------------------------------------

Introduction
------------

Field Programmable Gate Arrays now provide sufficient horsepower to implement
custom programmable hardware that operates on a scale of integration well
beyond the capabilities needed for this specification.

At least one INTV FPGA design solution exists that provides a single chip
solution for INTV hardware emulation, CPU, STIC and Sound.

The following proposed design dramatically enhances the INTV while keeping
deviations from the conceptual design of the existing FPGA solution to a
minimum.

This specification is preliminary and does not involve register level specifics.
Although additional ports are required to control the proposed new hardware
functions, adequate port space exists in the STIC memory map to manage the
specification.

This region has been tested on standard INTVs and no ports are currently mapped
to or phantom addressed in the proposed address range.

This specification offers the potential to enhance some existing  INTV games to
support enhanced graphics with a minimum of effort.


Overview
--------

 3 - Timers
   - Increased from 0

 4 - Interrupt sources
   - Increased from 1

 2 - Independently scrollable background 4 color background planes
   - Increased from 0

32 - 4 color Moveable Object Blocks - 4 banks of 8
   - Increased from 1 bank of 8 monochrome MOB's

 4 - Color background cards
   - Currently monochrome

 2 - Sound Chips
   - Increased from 1

 4 - IO ports
   - Increased from 2

 8 - Palette sets
   - Increased from 0

 Corrected smooth scrolling for card backgrounds

 Independent smooth scrolling for new background planes.

 Screen = view port onto a larger play field

 Mode Line support.

 Higher CPU clock speed.  1x 4x 16x

 De-phantomed memory map.

 Continuously addressable Card RAM and STIC ports.

 Digital video output for modern TV's rather than composite.

INTV Enhancements fall into several categories....

1. Hand Controllers

   INTV hand controller ports are obtained from two bi-directional parallel
   ports provided by the GI-??? Sound Chip.

   These ports are entirely adequate for their intended purpose and no real
   enhancements are required.

   However if the Sound System is enhanced as suggested below, two additional
   ports become available.

   Providing an additional two ports makes it possible to support 4 hand
   controllers, or provide support for alternative external hardware.


2. Sound Subsystem

   The INTV sound subsystem consists of a single GI->??? sound chip.

   Even though this chip provides 3 voices, this chip is really intended to
   provide flexible monophonic sound and noise.

   A second sound chip is included with the ECS.

   Enhancing the INTV by adding a second ECS compatible sound chip mapped to
   the standard address has obvious benefits.

   The clock input to the sound chip should come optionally from the STIC base
   clock or from one of the two proposed timer registers.


3. Interrupt System

   Currently the INTV has a single interrupt source that is triggered by the
   STIC vertical refresh circuitry and hence runs at a rate of 50 cycles per
   second (Pal) or 60 cycles per second (NTSC).

   This is only marginally adequate.

   The proposal is to have the INTV3 augmented with three additional interrupt
   sources.

   The first and second timer would be self resetting, 16 or 32 bit high speed
   timers that run independent of the video hardware.

   The third timer would come from a secondary count down timer that decrements
   with each hsync pulse from the STIC.

   If STIC registers are constantly available to the CPU, and updatable on the
   fly, the hsync interrupt would provide the the ability to implement inter-
   frame synchronization with the video, and specifically allow programmers to
   implement mode lines similar to those found on  8 bit ATARI systems.

   The alternate hardware timers would allow fixed interval times that are
   independent free from PAL/NTSC complications.  One timer should be used as
   an alternate clock for the sound circuitry, the other to provide general
   timing for note durations.


4. Video Hardware

   INTV graphics lacks the color depth and detail of other video game systems
   from it's era.

   Enhancements should therefore principally address that issue.

   Enhanced color:

   The easiest way to enhance the colors available in a system while
   maintaining backward compatibility with existing software is by re-tasking
   the bits used to specify a color so that they specify an entry into a
   palette register.

   In the case of the INTV a particularly effective enhancement would be to
   create a set of separate color palettes for individual objects and object
   types.

   For standard color mode:

   Palette 0 = (16 words) character foreground palette
   Palette 1 = (16 words) character background palette
   Palette 2 = (16 words) MOB_Set 0 Palette
   Palette 3 = (16 words) MOB_Set 1 Palette
   Palette 4 = (16 words) MOB_Set 2 Palette
   Palette 5 = (16 words) MOB_Set 3 Palette
   Palette 6 = (16 words) Background 0 Palette
   Palette 7 = (16 words) Background 1 Palette

   Palette entry definition = xxxx:rrrr:gggg:bbbb allows a total of 4096 colors

   Mob colors:

   It is proposed that the MOB count be increased from the current 8 to 32.
   This is to be accomplished by duplicating the circuitry for the the existing
   8 MOB's in the original INTV.

   This means that the MOB's will be organized as 4 banks of 8.  Hardware
   collision detection will be limited to detecting collisions between MOB's
   within each bank.

   Since MOB's obtain their memory from GRAM like the background tiles, it is
   proposed that MOB video be similarly enhanced to support 16 bit GRAM thereby
   providing 4 colors for each MOB or a single color MOB with a higher
   horizontal resolution.


   Background planes:

   It is proposed that two independent 4 color bit mapped background planes be
   implemented.

   These background planes are to be held in RAM that is external to the main
   system and visible to the system only though port reads and writes.

   It is further proposed that these video planes have configurable display
   priorities such that they can be placed anywhere in the z plane.

   It is further proposed that these video planes be scrollable so that
   parallax foreground background effects can be implemented.

   The planes are to be controlled through 6, 16 bit ports.

   Background Plane 0\1

   Port 0 (read/write) - Address in the external RAM to write to
   Port 1 (read/write) - The external RAM value at the port address.
   Port 2 (read/write) - Starting address of first byte displayed
   Port 3 (read/write) - Smooth scroll offset and mode selection.
   Port 4 (read/write) – Horizontal width
   Port 5 (read/write) – Starting address

   After each port read/write to pot 1, the hardware will increment it's
   address register, thereby allowing sequential read/writes from/to Port 1 to
   read/write sequential data from/to the external RAM.

   Backgrounds plane scan lines are to have a span that is larger than the
   horizontal screen size, and the starting address is to be configurable.

   These two features will allow background plane scrolling in both the
   horizontal and vertical direction.

   Smooth scrolling is controlled though a single smooth scrolling register.

   Plane 0 and Plane 1 are to live in their own 64K address space.

   This will allow for two background plains with a wide range of virtual
   horizontal and vertical resolutions.

   Gram:

   In the INTV, GRAM is 8 but RAM, and all tiles are 8 bits tall and wide.

   A potential enhancement would be to convert the GRAM into 16 bit RAM.

   Once the data is 16 bit, two new video output modes available.

   The first is to double the horizontal clock and walk out 16 bits instead of
   8. This would double the horizontal resolution from 160 to 320 horizontal
   dots.

   A second mode could be produced by clocking out only 8 bits from each 16 bit
   GRAM value, but combining bit 15 and bit 7, and using the bit pair to
   specify the color used.

   This will provide a 4 color mode with the same resolution as the original
   INTV.

   1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
   5 4 3 2 1
   |               |
   |               ------------------ Bit 0  Selects palette registers 0-3
   ---------------------------------- Bit 1

   There are currently only 64 re-definable GRAM cards in the INTV.  This is
   quite limited if complex games are  to be produced.  It is proposed that the
   GRAM space be increased to the full 256 cards that the backtab can support.

   STIC registers are to be made constantly available to the CPU so that STIC
   manipulation need not be performed only during the vblank interval.


   Backtab RAM:

   Backtab RAM is a block of RAM in the INTV that describes which GRAM images
   appear in each character character block on the screen as well as the
   foreground and background color used by the card.

   It is proposed that in the new video modes, the card data be regularized and
   extended as follows...

   1 1 1 1 1 1
   5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
   | | | | | | | | | | | | | | | |
   | | | | | | | | ----------------- GROM/GRAM card #
   | | | | | | | ------------------- RAM/ROM
   | | | --------------------------- Foreground Color
   --------------------------------- Background Color

   It is also proposed that the GRAM have a programmable width that can exceed
   the screen size as well as a programmable starting address so that scrolling
   in both the horizontal and virtual directions can be implemented.


5. Other enhancements

   Timers:

   Is is proposed that three separate 16 or 32 bit timers be added to the
   system.

   Timer1:

   This timer is a single shot count down timer driven by the video H-sync
   signal and should trigger an interrupt when it's count reaches zero.

   Implementing this timer will allow for the generation of mode line effects
   similar to those on the Atari series of computers.

   The second two timers should be driven by a fixed rate external clock that
   has a common frequency independent of PAL/NTSC video modes.

   It is intended that one of these timers be used for sound duration timing,
   and the second for independent timing specific to the game being written.


   Interrupts:

   It is proposed that interrupts be triggered from four separate sources.

   1. The Vsync
   2. Hsync timer
   3. Timer 1
   4. Timer 2

** Proposed Specification ends **

 

Forgive the bad formatting. 

 

I have heard of a handful of people who have worked on an Intellivision FPGA. I've been unsuccessful in contacting Dan from the video posted above. Any help being put in contact with capable people interested in being part of the development of this console, would be appreciated. 

 

Please contact me at elektronite@hotmail.com  

 

 

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1 minute ago, Rev said:

Perhaps contact @kevtris
 

Also, I wish you much success on this endeavor……...The elephant in the room to me is will this be crowdfunded? (Not to equate this to Amico, but the Intv community hasnt even healed from that disaster.)

 

Thanks!

No, this is not a crowdfunded project. The intention is to create a console and present it for sale. I'm pushing for an FPGA and cartridge based system. If it doesn't work out, it will be an emulated system similar to the Amiga minis that recently released. Obviously, the cartridge based system is preferred. 

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6 minutes ago, Games For Your Intellivision said:

No, this is not a crowdfunded project. The intention is to create a console and present it for sale. I'm pushing for an FPGA and cartridge based system. If it doesn't work out, it will be an emulated system similar to the Amiga minis that recently released. Obviously, the cartridge based system is preferred. 


Good news! 
 

If this gets off the ground Ill donate a couple of games to be included on the system, if wanted. 
 

(depending on IP) 😝

Edited by Rev
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